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-rw-r--r--clang/lib/Basic/Diagnostic.cpp2
-rw-r--r--clang/lib/Basic/DiagnosticIDs.cpp4
-rw-r--r--clang/lib/Basic/LangOptions.cpp1
-rw-r--r--clang/lib/Basic/SourceManager.cpp4
-rw-r--r--clang/lib/Basic/TargetInfo.cpp2
-rw-r--r--clang/lib/Basic/Targets/AArch64.cpp2
-rw-r--r--clang/lib/Basic/Targets/AMDGPU.cpp7
-rw-r--r--clang/lib/Basic/Targets/ARM.cpp8
-rw-r--r--clang/lib/Basic/Targets/AVR.h2
-rw-r--r--clang/lib/Basic/Targets/DirectX.h2
-rw-r--r--clang/lib/Basic/Targets/Hexagon.cpp2
-rw-r--r--clang/lib/Basic/Targets/LoongArch.cpp2
-rw-r--r--clang/lib/Basic/Targets/NVPTX.cpp15
-rw-r--r--clang/lib/Basic/Targets/OSTargets.h3
-rw-r--r--clang/lib/Basic/Targets/PPC.cpp2
-rw-r--r--clang/lib/Basic/Targets/RISCV.cpp2
-rw-r--r--clang/lib/Basic/Targets/SPIR.h15
-rw-r--r--clang/lib/Basic/Targets/SystemZ.h2
-rw-r--r--clang/lib/Basic/Targets/X86.cpp5
19 files changed, 51 insertions, 31 deletions
diff --git a/clang/lib/Basic/Diagnostic.cpp b/clang/lib/Basic/Diagnostic.cpp
index e33e843..dc3778b 100644
--- a/clang/lib/Basic/Diagnostic.cpp
+++ b/clang/lib/Basic/Diagnostic.cpp
@@ -664,6 +664,8 @@ void DiagnosticsEngine::Report(const StoredDiagnostic &storedDiag) {
void DiagnosticsEngine::Report(Level DiagLevel, const Diagnostic &Info) {
assert(DiagLevel != Ignored && "Cannot emit ignored diagnostics!");
+ assert(!getDiagnosticIDs()->isTrapDiag(Info.getID()) &&
+ "Trap diagnostics should not be consumed by the DiagnosticsEngine");
Client->HandleDiagnostic(DiagLevel, Info);
if (Client->IncludeInDiagnosticCounts()) {
if (DiagLevel == Warning)
diff --git a/clang/lib/Basic/DiagnosticIDs.cpp b/clang/lib/Basic/DiagnosticIDs.cpp
index 73f24a82..a1d9d0f 100644
--- a/clang/lib/Basic/DiagnosticIDs.cpp
+++ b/clang/lib/Basic/DiagnosticIDs.cpp
@@ -69,6 +69,7 @@ enum DiagnosticClass {
CLASS_WARNING = DiagnosticIDs::CLASS_WARNING,
CLASS_EXTENSION = DiagnosticIDs::CLASS_EXTENSION,
CLASS_ERROR = DiagnosticIDs::CLASS_ERROR,
+ CLASS_TRAP = DiagnosticIDs::CLASS_TRAP,
};
struct StaticDiagInfoRec {
@@ -139,6 +140,7 @@ VALIDATE_DIAG_SIZE(SEMA)
VALIDATE_DIAG_SIZE(ANALYSIS)
VALIDATE_DIAG_SIZE(REFACTORING)
VALIDATE_DIAG_SIZE(INSTALLAPI)
+VALIDATE_DIAG_SIZE(TRAP)
#undef VALIDATE_DIAG_SIZE
#undef STRINGIFY_NAME
@@ -171,6 +173,7 @@ const StaticDiagInfoRec StaticDiagInfo[] = {
#include "clang/Basic/DiagnosticAnalysisKinds.inc"
#include "clang/Basic/DiagnosticRefactoringKinds.inc"
#include "clang/Basic/DiagnosticInstallAPIKinds.inc"
+#include "clang/Basic/DiagnosticTrapKinds.inc"
// clang-format on
#undef DIAG
};
@@ -214,6 +217,7 @@ CATEGORY(SEMA, CROSSTU)
CATEGORY(ANALYSIS, SEMA)
CATEGORY(REFACTORING, ANALYSIS)
CATEGORY(INSTALLAPI, REFACTORING)
+CATEGORY(TRAP, INSTALLAPI)
#undef CATEGORY
// Avoid out of bounds reads.
diff --git a/clang/lib/Basic/LangOptions.cpp b/clang/lib/Basic/LangOptions.cpp
index 9c14a25..f034514 100644
--- a/clang/lib/Basic/LangOptions.cpp
+++ b/clang/lib/Basic/LangOptions.cpp
@@ -128,6 +128,7 @@ void LangOptions::setLangDefaults(LangOptions &Opts, Language Lang,
Opts.WChar = Std.isCPlusPlus();
Opts.Digraphs = Std.hasDigraphs();
Opts.RawStringLiterals = Std.hasRawStringLiterals();
+ Opts.NamedLoops = Std.isC2y();
Opts.HLSL = Lang == Language::HLSL;
if (Opts.HLSL && Opts.IncludeDefaultHeader)
diff --git a/clang/lib/Basic/SourceManager.cpp b/clang/lib/Basic/SourceManager.cpp
index 343c26e..d8ec837 100644
--- a/clang/lib/Basic/SourceManager.cpp
+++ b/clang/lib/Basic/SourceManager.cpp
@@ -1171,14 +1171,14 @@ unsigned SourceManager::getColumnNumber(FileID FID, unsigned FilePos,
if (Buf[FilePos - 1] == '\r' || Buf[FilePos - 1] == '\n')
--FilePos;
}
- return FilePos - LineStart + 1;
+ return (FilePos - LineStart) + 1;
}
}
unsigned LineStart = FilePos;
while (LineStart && Buf[LineStart-1] != '\n' && Buf[LineStart-1] != '\r')
--LineStart;
- return FilePos-LineStart+1;
+ return (FilePos - LineStart) + 1;
}
// isInvalid - Return the result of calling loc.isInvalid(), and
diff --git a/clang/lib/Basic/TargetInfo.cpp b/clang/lib/Basic/TargetInfo.cpp
index 21fc084..2fbf1ee 100644
--- a/clang/lib/Basic/TargetInfo.cpp
+++ b/clang/lib/Basic/TargetInfo.cpp
@@ -62,7 +62,7 @@ TargetInfo::TargetInfo(const llvm::Triple &T) : Triple(T) {
TLSSupported = true;
VLASupported = true;
NoAsmVariants = false;
- HasLegalHalfType = false;
+ HasFastHalfType = false;
HalfArgsAndReturns = false;
HasFloat128 = false;
HasIbm128 = false;
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index 2b023e5..9e03a08 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -142,7 +142,7 @@ AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple,
AddrSpaceMap = &ARM64AddrSpaceMap;
// All AArch64 implementations support ARMv8 FP, which makes half a legal type.
- HasLegalHalfType = true;
+ HasFastHalfType = true;
HalfArgsAndReturns = true;
HasFloat16 = true;
HasStrictFP = true;
diff --git a/clang/lib/Basic/Targets/AMDGPU.cpp b/clang/lib/Basic/Targets/AMDGPU.cpp
index 52cbdbc..87de9e6 100644
--- a/clang/lib/Basic/Targets/AMDGPU.cpp
+++ b/clang/lib/Basic/Targets/AMDGPU.cpp
@@ -197,12 +197,11 @@ bool AMDGPUTargetInfo::initFeatureMap(
const std::vector<std::string> &FeatureVec) const {
using namespace llvm::AMDGPU;
- fillAMDGPUFeatureMap(CPU, getTriple(), Features);
+
if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec))
return false;
- // TODO: Should move this logic into TargetParser
- auto HasError = insertWaveSizeFeature(CPU, getTriple(), Features);
+ auto HasError = fillAMDGPUFeatureMap(CPU, getTriple(), Features);
switch (HasError.first) {
default:
break;
@@ -251,7 +250,7 @@ AMDGPUTargetInfo::AMDGPUTargetInfo(const llvm::Triple &Triple,
BFloat16Format = &llvm::APFloat::BFloat();
}
- HasLegalHalfType = true;
+ HasFastHalfType = true;
HasFloat16 = true;
WavefrontSize = (GPUFeatures & llvm::AMDGPU::FEATURE_WAVE32) ? 32 : 64;
diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp
index 75fdf38..3de17d2 100644
--- a/clang/lib/Basic/Targets/ARM.cpp
+++ b/clang/lib/Basic/Targets/ARM.cpp
@@ -585,13 +585,13 @@ bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
} else if (Feature == "+fp16") {
HW_FP |= HW_FP_HP;
} else if (Feature == "+fullfp16") {
- HasLegalHalfType = true;
+ HasFastHalfType = true;
} else if (Feature == "+dotprod") {
DotProd = true;
} else if (Feature == "+mve") {
MVE |= MVE_INT;
} else if (Feature == "+mve.fp") {
- HasLegalHalfType = true;
+ HasFastHalfType = true;
FPU |= FPARMV8;
MVE |= MVE_INT | MVE_FP;
HW_FP |= HW_FP_SP | HW_FP_HP;
@@ -1014,11 +1014,11 @@ void ARMTargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__ARM_FP_FAST", "1");
// Armv8.2-A FP16 vector intrinsic
- if ((FPU & NeonFPU) && HasLegalHalfType)
+ if ((FPU & NeonFPU) && HasFastHalfType)
Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1");
// Armv8.2-A FP16 scalar intrinsics
- if (HasLegalHalfType)
+ if (HasFastHalfType)
Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1");
// Armv8.2-A dot product intrinsics
diff --git a/clang/lib/Basic/Targets/AVR.h b/clang/lib/Basic/Targets/AVR.h
index 75c969f..b6667786 100644
--- a/clang/lib/Basic/Targets/AVR.h
+++ b/clang/lib/Basic/Targets/AVR.h
@@ -57,7 +57,7 @@ public:
Int16Type = SignedInt;
Char32Type = UnsignedLong;
SigAtomicType = SignedChar;
- resetDataLayout("e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8");
+ resetDataLayout("e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8:16-a:8");
}
void getTargetDefines(const LangOptions &Opts,
diff --git a/clang/lib/Basic/Targets/DirectX.h b/clang/lib/Basic/Targets/DirectX.h
index 17240cf..bd13c9e 100644
--- a/clang/lib/Basic/Targets/DirectX.h
+++ b/clang/lib/Basic/Targets/DirectX.h
@@ -59,7 +59,7 @@ public:
VLASupported = false;
AddrSpaceMap = &DirectXAddrSpaceMap;
UseAddrSpaceMapMangling = true;
- HasLegalHalfType = true;
+ HasFastHalfType = true;
HasFloat16 = true;
NoAsmVariants = true;
PlatformMinVersion = Triple.getOSVersion();
diff --git a/clang/lib/Basic/Targets/Hexagon.cpp b/clang/lib/Basic/Targets/Hexagon.cpp
index 06dcac0..cea64f9 100644
--- a/clang/lib/Basic/Targets/Hexagon.cpp
+++ b/clang/lib/Basic/Targets/Hexagon.cpp
@@ -149,7 +149,7 @@ bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasAudio = true;
}
if (CPU.compare("hexagonv68") >= 0) {
- HasLegalHalfType = true;
+ HasFastHalfType = true;
HasFloat16 = true;
}
return true;
diff --git a/clang/lib/Basic/Targets/LoongArch.cpp b/clang/lib/Basic/Targets/LoongArch.cpp
index f6915df..8e29bb7 100644
--- a/clang/lib/Basic/Targets/LoongArch.cpp
+++ b/clang/lib/Basic/Targets/LoongArch.cpp
@@ -461,6 +461,8 @@ LoongArchTargetInfo::parseTargetAttr(StringRef Features) const {
case AttrFeatureKind::Feature:
Ret.Features.push_back("+" + Value.str());
+ if (Value == "lasx")
+ Ret.Features.push_back("+lsx");
break;
}
}
diff --git a/clang/lib/Basic/Targets/NVPTX.cpp b/clang/lib/Basic/Targets/NVPTX.cpp
index 79995cc..f7abc05 100644
--- a/clang/lib/Basic/Targets/NVPTX.cpp
+++ b/clang/lib/Basic/Targets/NVPTX.cpp
@@ -65,18 +65,19 @@ NVPTXTargetInfo::NVPTXTargetInfo(const llvm::Triple &Triple,
GPU = OffloadArch::UNUSED;
// PTX supports f16 as a fundamental type.
- HasLegalHalfType = true;
+ HasFastHalfType = true;
HasFloat16 = true;
if (TargetPointerWidth == 32)
- resetDataLayout(
- "e-p:32:32-p6:32:32-p7:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64");
+ resetDataLayout("e-p:32:32-p6:32:32-p7:32:32-i64:64-i128:128-i256:256-v16:"
+ "16-v32:32-n16:32:64");
else if (Opts.NVPTXUseShortPointers)
- resetDataLayout(
- "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-p7:32:32-i64:64-i128:128-v16:"
- "16-v32:32-n16:32:64");
+ resetDataLayout("e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-p7:32:32-i64:64-"
+ "i128:128-i256:256-v16:"
+ "16-v32:32-n16:32:64");
else
- resetDataLayout("e-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64");
+ resetDataLayout(
+ "e-p6:32:32-i64:64-i128:128-i256:256-v16:16-v32:32-n16:32:64");
// If possible, get a TargetInfo for our host triple, so we can match its
// types.
diff --git a/clang/lib/Basic/Targets/OSTargets.h b/clang/lib/Basic/Targets/OSTargets.h
index 94b018a..a733f6e 100644
--- a/clang/lib/Basic/Targets/OSTargets.h
+++ b/clang/lib/Basic/Targets/OSTargets.h
@@ -174,6 +174,9 @@ protected:
DefineStd(Builder, "unix", Opts);
if (this->HasFloat128)
Builder.defineMacro("__FLOAT128__");
+
+ if (Opts.C11)
+ Builder.defineMacro("__STDC_NO_THREADS__");
}
public:
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index ef18354..a6e1ad10 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -89,6 +89,8 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
}
static void defineXLCompatMacros(MacroBuilder &Builder) {
+ Builder.defineMacro("__builtin_bcdcopysign", "__builtin_ppc_bcdcopysign");
+ Builder.defineMacro("__builtin_bcdsetsign", "__builtin_ppc_bcdsetsign");
Builder.defineMacro("__builtin_national2packed",
"__builtin_ppc_national2packed");
Builder.defineMacro("__builtin_packed2national",
diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
index a6a5ec4..04da4e6 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -427,7 +427,7 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
ABI = ISAInfo->computeDefaultABI().str();
if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx"))
- HasLegalHalfType = true;
+ HasFastHalfType = true;
FastScalarUnalignedAccess =
llvm::is_contained(Features, "+unaligned-scalar-mem");
diff --git a/clang/lib/Basic/Targets/SPIR.h b/clang/lib/Basic/Targets/SPIR.h
index c13b286..8bb0428 100644
--- a/clang/lib/Basic/Targets/SPIR.h
+++ b/clang/lib/Basic/Targets/SPIR.h
@@ -106,7 +106,7 @@ protected:
LongWidth = LongAlign = 64;
AddrSpaceMap = &SPIRDefIsPrivMap;
UseAddrSpaceMapMangling = true;
- HasLegalHalfType = true;
+ HasFastHalfType = true;
HasFloat16 = true;
// Define available target features
// These must be defined in sorted order!
@@ -219,8 +219,11 @@ public:
setAddressSpaceMap(
/*DefaultIsGeneric=*/Opts.SYCLIsDevice ||
// The address mapping from HIP/CUDA language for device code is only
- // defined for SPIR-V.
- (getTriple().isSPIRV() && Opts.CUDAIsDevice));
+ // defined for SPIR-V, and all Intel SPIR-V code should have the default
+ // AS as generic.
+ (getTriple().isSPIRV() &&
+ (Opts.CUDAIsDevice ||
+ getTriple().getVendor() == llvm::Triple::Intel)));
}
void setSupportedOpenCLOpts() override {
@@ -427,7 +430,7 @@ public:
BFloat16Width = BFloat16Align = 16;
BFloat16Format = &llvm::APFloat::BFloat();
- HasLegalHalfType = true;
+ HasFastHalfType = true;
HasFloat16 = true;
HalfArgsAndReturns = true;
@@ -438,6 +441,10 @@ public:
ArrayRef<const char *> getGCCRegNames() const override;
+ BuiltinVaListKind getBuiltinVaListKind() const override {
+ return TargetInfo::CharPtrBuiltinVaList;
+ }
+
bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
StringRef,
const std::vector<std::string> &) const override;
diff --git a/clang/lib/Basic/Targets/SystemZ.h b/clang/lib/Basic/Targets/SystemZ.h
index 7f7dcf8..dc2185e 100644
--- a/clang/lib/Basic/Targets/SystemZ.h
+++ b/clang/lib/Basic/Targets/SystemZ.h
@@ -104,7 +104,7 @@ public:
// -ffloat16-excess-precision=none is given, no conversions will be made
// and instead the backend will promote each half operation to float
// individually.
- HasLegalHalfType = false;
+ HasFastHalfType = false;
HasStrictFP = true;
}
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 24ecec2..f9424cb 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -348,7 +348,7 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasAVX512BF16 = true;
} else if (Feature == "+avx512fp16") {
HasAVX512FP16 = true;
- HasLegalHalfType = true;
+ HasFastHalfType = true;
} else if (Feature == "+avx512dq") {
HasAVX512DQ = true;
} else if (Feature == "+avx512bitalg") {
@@ -1029,8 +1029,7 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__CF__");
if (HasZU)
Builder.defineMacro("__ZU__");
- if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD && HasCCMP && HasNF &&
- HasCF && HasZU)
+ if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD && HasCCMP && HasNF && HasZU)
Builder.defineMacro("__APX_F__");
if (HasEGPR && HasInlineAsmUseGPR32)
Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__");
generated by cgit v1.1 at 2025-09-03 21:30:17 +0000