diff options
Diffstat (limited to 'clang/lib/Basic/Targets')
-rw-r--r-- | clang/lib/Basic/Targets/AArch64.cpp | 3 | ||||
-rw-r--r-- | clang/lib/Basic/Targets/AArch64.h | 2 | ||||
-rw-r--r-- | clang/lib/Basic/Targets/AMDGPU.cpp | 7 | ||||
-rw-r--r-- | clang/lib/Basic/Targets/ARM.cpp | 10 | ||||
-rw-r--r-- | clang/lib/Basic/Targets/ARM.h | 9 | ||||
-rw-r--r-- | clang/lib/Basic/Targets/RISCV.cpp | 9 | ||||
-rw-r--r-- | clang/lib/Basic/Targets/RISCV.h | 2 | ||||
-rw-r--r-- | clang/lib/Basic/Targets/WebAssembly.cpp | 16 | ||||
-rw-r--r-- | clang/lib/Basic/Targets/WebAssembly.h | 1 | ||||
-rw-r--r-- | clang/lib/Basic/Targets/X86.cpp | 8 | ||||
-rw-r--r-- | clang/lib/Basic/Targets/X86.h | 2 |
11 files changed, 43 insertions, 26 deletions
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp index 72d2e5f..2b023e5 100644 --- a/clang/lib/Basic/Targets/AArch64.cpp +++ b/clang/lib/Basic/Targets/AArch64.cpp @@ -786,7 +786,8 @@ AArch64TargetInfo::getVScaleRange(const LangOptions &LangOpts, return std::nullopt; } -uint64_t AArch64TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const { +llvm::APInt +AArch64TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const { return llvm::AArch64::getFMVPriority(Features); } diff --git a/clang/lib/Basic/Targets/AArch64.h b/clang/lib/Basic/Targets/AArch64.h index f4277e9..dfd89be 100644 --- a/clang/lib/Basic/Targets/AArch64.h +++ b/clang/lib/Basic/Targets/AArch64.h @@ -152,7 +152,7 @@ public: void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; bool setCPU(const std::string &Name) override; - uint64_t getFMVPriority(ArrayRef<StringRef> Features) const override; + llvm::APInt getFMVPriority(ArrayRef<StringRef> Features) const override; bool useFP16ConversionIntrinsics() const override { return false; diff --git a/clang/lib/Basic/Targets/AMDGPU.cpp b/clang/lib/Basic/Targets/AMDGPU.cpp index cebcfa3..52cbdbc 100644 --- a/clang/lib/Basic/Targets/AMDGPU.cpp +++ b/clang/lib/Basic/Targets/AMDGPU.cpp @@ -266,8 +266,11 @@ AMDGPUTargetInfo::AMDGPUTargetInfo(const llvm::Triple &Triple, MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; CUMode = !(GPUFeatures & llvm::AMDGPU::FEATURE_WGP); - for (auto F : {"image-insts", "gws", "vmem-to-lds-load-insts"}) - ReadOnlyFeatures.insert(F); + + for (auto F : {"image-insts", "gws", "vmem-to-lds-load-insts"}) { + if (GPUKind != llvm::AMDGPU::GK_NONE) + ReadOnlyFeatures.insert(F); + } HalfArgsAndReturns = true; } diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp index 29de34bb..6bec2fa 100644 --- a/clang/lib/Basic/Targets/ARM.cpp +++ b/clang/lib/Basic/Targets/ARM.cpp @@ -618,21 +618,21 @@ bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, LDREX = 0; else if (ArchKind == llvm::ARM::ArchKind::ARMV6K || ArchKind == llvm::ARM::ArchKind::ARMV6KZ) - LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B; + LDREX = ARM_LDREX_D | ARM_LDREX_W | ARM_LDREX_H | ARM_LDREX_B; else - LDREX = LDREX_W; + LDREX = ARM_LDREX_W; break; case 7: case 8: if (ArchProfile == llvm::ARM::ProfileKind::M) - LDREX = LDREX_W | LDREX_H | LDREX_B; + LDREX = ARM_LDREX_W | ARM_LDREX_H | ARM_LDREX_B; else - LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B; + LDREX = ARM_LDREX_D | ARM_LDREX_W | ARM_LDREX_H | ARM_LDREX_B; break; case 9: assert(ArchProfile != llvm::ARM::ProfileKind::M && "No Armv9-M architectures defined"); - LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B; + LDREX = ARM_LDREX_D | ARM_LDREX_W | ARM_LDREX_H | ARM_LDREX_B; } if (!(FPU & NeonFPU) && FPMath == FP_Neon) { diff --git a/clang/lib/Basic/Targets/ARM.h b/clang/lib/Basic/Targets/ARM.h index 1719217..43c4718 100644 --- a/clang/lib/Basic/Targets/ARM.h +++ b/clang/lib/Basic/Targets/ARM.h @@ -98,13 +98,6 @@ class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public TargetInfo { LLVM_PREFERRED_TYPE(bool) unsigned HasBTI : 1; - enum { - LDREX_B = (1 << 0), /// byte (8-bit) - LDREX_H = (1 << 1), /// half (16-bit) - LDREX_W = (1 << 2), /// word (32-bit) - LDREX_D = (1 << 3), /// double (64-bit) - }; - uint32_t LDREX; // ACLE 6.5.1 Hardware floating point @@ -225,6 +218,8 @@ public: bool hasBitIntType() const override { return true; } + unsigned getARMLDREXMask() const override { return LDREX; } + const char *getBFloat16Mangling() const override { return "u6__bf16"; }; std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override { diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index 8a28c07..a6a5ec4 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -568,7 +568,8 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const { return Ret; } -uint64_t RISCVTargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const { +llvm::APInt +RISCVTargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const { // Priority is explicitly specified on RISC-V unlike on other targets, where // it is derived by all the features of a specific version. Therefore if a // feature contains the priority string, then return it immediately. @@ -580,12 +581,12 @@ uint64_t RISCVTargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const { Feature = RHS; else continue; - uint64_t Priority; + unsigned Priority; if (!Feature.getAsInteger(0, Priority)) - return Priority; + return llvm::APInt(32, Priority); } // Default Priority is zero. - return 0; + return llvm::APInt::getZero(32); } TargetInfo::CallingConvCheckResult diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h index 8d629ab..58bfad1 100644 --- a/clang/lib/Basic/Targets/RISCV.h +++ b/clang/lib/Basic/Targets/RISCV.h @@ -123,7 +123,7 @@ public: void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override; bool supportsTargetAttributeTune() const override { return true; } ParsedTargetAttr parseTargetAttr(StringRef Str) const override; - uint64_t getFMVPriority(ArrayRef<StringRef> Features) const override; + llvm::APInt getFMVPriority(ArrayRef<StringRef> Features) const override; std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override { return std::make_pair(32, 32); diff --git a/clang/lib/Basic/Targets/WebAssembly.cpp b/clang/lib/Basic/Targets/WebAssembly.cpp index af25d25..e362350e 100644 --- a/clang/lib/Basic/Targets/WebAssembly.cpp +++ b/clang/lib/Basic/Targets/WebAssembly.cpp @@ -64,6 +64,7 @@ bool WebAssemblyTargetInfo::hasFeature(StringRef Feature) const { .Case("mutable-globals", HasMutableGlobals) .Case("nontrapping-fptoint", HasNontrappingFPToInt) .Case("reference-types", HasReferenceTypes) + .Case("gc", HasGC) .Case("relaxed-simd", SIMDLevel >= RelaxedSIMD) .Case("sign-ext", HasSignExt) .Case("simd128", SIMDLevel >= SIMD128) @@ -106,6 +107,8 @@ void WebAssemblyTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__wasm_nontrapping_fptoint__"); if (HasReferenceTypes) Builder.defineMacro("__wasm_reference_types__"); + if (HasGC) + Builder.defineMacro("__wasm_gc__"); if (SIMDLevel >= RelaxedSIMD) Builder.defineMacro("__wasm_relaxed_simd__"); if (HasSignExt) @@ -307,6 +310,14 @@ bool WebAssemblyTargetInfo::handleTargetFeatures( HasReferenceTypes = false; continue; } + if (Feature == "+gc") { + HasGC = true; + continue; + } + if (Feature == "-gc") { + HasGC = false; + continue; + } if (Feature == "+relaxed-simd") { SIMDLevel = std::max(SIMDLevel, RelaxedSIMD); continue; @@ -353,6 +364,11 @@ bool WebAssemblyTargetInfo::handleTargetFeatures( return false; } + // gc implies reference-types + if (HasGC) { + HasReferenceTypes = true; + } + // bulk-memory-opt is a subset of bulk-memory. if (HasBulkMemory) { HasBulkMemoryOpt = true; diff --git a/clang/lib/Basic/Targets/WebAssembly.h b/clang/lib/Basic/Targets/WebAssembly.h index 57b366c..c47c8cc 100644 --- a/clang/lib/Basic/Targets/WebAssembly.h +++ b/clang/lib/Basic/Targets/WebAssembly.h @@ -69,6 +69,7 @@ class LLVM_LIBRARY_VISIBILITY WebAssemblyTargetInfo : public TargetInfo { bool HasMutableGlobals = false; bool HasNontrappingFPToInt = false; bool HasReferenceTypes = false; + bool HasGC = false; bool HasSignExt = false; bool HasTailCall = false; bool HasWideArithmetic = false; diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp index a1f5aa2..24ecec2 100644 --- a/clang/lib/Basic/Targets/X86.cpp +++ b/clang/lib/Basic/Targets/X86.cpp @@ -1390,8 +1390,8 @@ static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { // correct, so it asserts if the value is out of range. } -uint64_t X86TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const { - auto getPriority = [](StringRef Feature) -> uint64_t { +llvm::APInt X86TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const { + auto getPriority = [](StringRef Feature) -> unsigned { // Valid CPUs have a 'key feature' that compares just better than its key // feature. using namespace llvm::X86; @@ -1405,11 +1405,11 @@ uint64_t X86TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const { return getFeaturePriority(getFeature(Feature)) << 1; }; - uint64_t Priority = 0; + unsigned Priority = 0; for (StringRef Feature : Features) if (!Feature.empty()) Priority = std::max(Priority, getPriority(Feature)); - return Priority; + return llvm::APInt(32, Priority); } bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h index ebc59c9..eb15103 100644 --- a/clang/lib/Basic/Targets/X86.h +++ b/clang/lib/Basic/Targets/X86.h @@ -388,7 +388,7 @@ public: return CPU != llvm::X86::CK_None; } - uint64_t getFMVPriority(ArrayRef<StringRef> Features) const override; + llvm::APInt getFMVPriority(ArrayRef<StringRef> Features) const override; bool setFPMath(StringRef Name) override; |