diff options
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 400 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td | 28 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVMCInstLower.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll | 6 |
8 files changed, 277 insertions, 187 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index a41b04d..66324f7 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -90,6 +90,33 @@ def MxList { list<LMULInfo> m = [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8]; } +class FPR_Info<RegisterClass regclass, string fx> { + RegisterClass fprclass = regclass; + string FX = fx; +} + +def SCALAR_F16 : FPR_Info<FPR16, "F16">; +def SCALAR_F32 : FPR_Info<FPR32, "F32">; +def SCALAR_F64 : FPR_Info<FPR64, "F64">; + +def FPList { + list<FPR_Info> fpinfo = [SCALAR_F16, SCALAR_F32, SCALAR_F64]; +} + +class getScalarSuffix<ValueType type> { + string suffix = !cond(!eq(type, XLenVT): "VX", + !eq(type, f16): "VF_F16", + !eq(type, f32): "VF_F32", + !eq(type, f64): "VF_F64"); +} + +class getWScalarSuffix<ValueType type> { + string suffix = !cond(!eq(type, XLenVT): "WX", + !eq(type, f16): "WF_F16", + !eq(type, f32): "WF_F32", + !eq(type, f64): "WF_F64"); +} + class MxSet<int eew> { list<LMULInfo> m = !cond(!eq(eew, 8) : [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8], !eq(eew, 16) : [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8], @@ -135,18 +162,6 @@ def VLMax : OutPatFrag<(ops), (XLenVT X0)>; // List of EEW. defvar EEWList = [8, 16, 32, 64]; -// We only model FPR32 for V instructions in RISCVInstrInfoV.td. -// FP16/FP32/FP64 registers are alias each other. Convert FPR16 and FPR64 -// to FPR32 for V instructions is enough. -class ToFPR32<ValueType type, DAGOperand operand, string name> { - dag ret = !cond(!eq(!cast<string>(operand), !cast<string>(FPR64)): - (EXTRACT_SUBREG !dag(type, [FPR64], [name]), sub_32), - !eq(!cast<string>(operand), !cast<string>(FPR16)): - (SUBREG_TO_REG (i16 -1), !dag(type, [FPR16], [name]), sub_16), - !eq(1, 1): - !dag(type, [operand], [name])); -} - class SegRegClass<LMULInfo m, int nf> { VReg RC = !cast<VReg>("VRN" # nf # !cond(!eq(m.value, V_MF8.value): V_M1.MX, !eq(m.value, V_MF4.value): V_M1.MX, @@ -452,7 +467,10 @@ class PseudoToVInst<string PseudoInst> { !subst("_B32", "", !subst("_B64", "", !subst("_MASK", "", - !subst("Pseudo", "", PseudoInst)))))))))))))))); + !subst("_F16", "", + !subst("_F32", "", + !subst("_F64", "", + !subst("Pseudo", "", PseudoInst))))))))))))))))))); } class ToLowerCase<string Upper> { @@ -1382,10 +1400,16 @@ multiclass VPseudoBinaryV_VV_EEW<int eew, string Constraint = ""> { } } -multiclass VPseudoBinaryV_VX<bit IsFloat, string Constraint = ""> { +multiclass VPseudoBinaryV_VX<string Constraint = ""> { + foreach m = MxList.m in + defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint>; +} + +multiclass VPseudoBinaryV_VF<string Constraint = ""> { foreach m = MxList.m in - defm !if(IsFloat, "_VF", "_VX") : VPseudoBinary<m.vrclass, m.vrclass, - !if(IsFloat, FPR32, GPR), m, Constraint>; + foreach f = FPList.fpinfo in + defm "_VF_" # f.FX : VPseudoBinary<m.vrclass, m.vrclass, + f.fprclass, m, Constraint>; } multiclass VPseudoBinaryV_VI<Operand ImmType = simm5, string Constraint = ""> { @@ -1413,11 +1437,18 @@ multiclass VPseudoBinaryW_VV { "@earlyclobber $rd">; } -multiclass VPseudoBinaryW_VX<bit IsFloat> { +multiclass VPseudoBinaryW_VX { foreach m = MxList.m[0-5] in - defm !if(IsFloat, "_VF", "_VX") : VPseudoBinary<m.wvrclass, m.vrclass, - !if(IsFloat, FPR32, GPR), m, - "@earlyclobber $rd">; + defm "_VX" : VPseudoBinary<m.wvrclass, m.vrclass, GPR, m, + "@earlyclobber $rd">; +} + +multiclass VPseudoBinaryW_VF { + foreach m = MxList.m[0-5] in + foreach f = FPList.fpinfo[0-1] in + defm "_VF_" # f.FX : VPseudoBinary<m.wvrclass, m.vrclass, + f.fprclass, m, + "@earlyclobber $rd">; } multiclass VPseudoBinaryW_WV { @@ -1426,11 +1457,18 @@ multiclass VPseudoBinaryW_WV { "@earlyclobber $rd">; } -multiclass VPseudoBinaryW_WX<bit IsFloat> { +multiclass VPseudoBinaryW_WX { foreach m = MxList.m[0-5] in - defm !if(IsFloat, "_WF", "_WX") : VPseudoBinary<m.wvrclass, m.wvrclass, - !if(IsFloat, FPR32, GPR), m, - "@earlyclobber $rd">; + defm "_WX" : VPseudoBinary<m.wvrclass, m.wvrclass, GPR, m, + "@earlyclobber $rd">; +} + +multiclass VPseudoBinaryW_WF { + foreach m = MxList.m[0-5] in + foreach f = FPList.fpinfo[0-1] in + defm "_WF_" # f.FX : VPseudoBinary<m.wvrclass, m.wvrclass, + f.fprclass, m, + "@earlyclobber $rd">; } multiclass VPseudoBinaryV_WV { @@ -1465,14 +1503,21 @@ multiclass VPseudoBinaryV_VM<bit CarryOut = 0, bit CarryIn = 1, } multiclass VPseudoBinaryV_XM<bit CarryOut = 0, bit CarryIn = 1, - string Constraint = "", bit IsFloat = 0> { + string Constraint = ""> { foreach m = MxList.m in - def !if(IsFloat, "_VF", "_VX") # !if(CarryIn, "M", "") # "_" # m.MX : + def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX : VPseudoBinaryCarryIn<!if(CarryOut, VR, !if(!and(CarryIn, !not(CarryOut)), GetVRegNoV0<m.vrclass>.R, m.vrclass)), - m.vrclass, !if(IsFloat, FPR32, GPR), - m, CarryIn, Constraint>; + m.vrclass, GPR, m, CarryIn, Constraint>; +} + +multiclass VPseudoBinaryV_FM { + foreach m = MxList.m in + foreach f = FPList.fpinfo in + def "_VFM_" # f.FX # "_" # m.MX : + VPseudoBinaryCarryIn<GetVRegNoV0<m.vrclass>.R, + m.vrclass, f.fprclass, m, /*CarryIn=*/1, "">; } multiclass VPseudoBinaryV_IM<bit CarryOut = 0, bit CarryIn = 1, @@ -1497,8 +1542,10 @@ multiclass VPseudoUnaryV_V_X_I_NoDummyMask { multiclass VPseudoUnaryV_F_NoDummyMask { foreach m = MxList.m in { - let VLMul = m.value in { - def "_F_" # m.MX : VPseudoUnaryNoDummyMask<m.vrclass, FPR32>; + foreach f = FPList.fpinfo in { + let VLMul = m.value in { + def "_F_" # f.FX # "_" # m.MX : VPseudoUnaryNoDummyMask<m.vrclass, f.fprclass>; + } } } } @@ -1557,11 +1604,17 @@ multiclass VPseudoBinaryM_VV { defm _VV : VPseudoBinary<VR, m.vrclass, m.vrclass, m, "@earlyclobber $rd">; } -multiclass VPseudoBinaryM_VX<bit IsFloat> { +multiclass VPseudoBinaryM_VX { + foreach m = MxList.m in + defm "_VX" : + VPseudoBinary<VR, m.vrclass, GPR, m, "@earlyclobber $rd">; +} + +multiclass VPseudoBinaryM_VF { foreach m = MxList.m in - defm !if(IsFloat, "_VF", "_VX") : - VPseudoBinary<VR, m.vrclass, !if(IsFloat, FPR32, GPR), m, - "@earlyclobber $rd">; + foreach f = FPList.fpinfo in + defm "_VF_" # f.FX : + VPseudoBinary<VR, m.vrclass, f.fprclass, m, "@earlyclobber $rd">; } multiclass VPseudoBinaryM_VI { @@ -1571,28 +1624,43 @@ multiclass VPseudoBinaryM_VI { multiclass VPseudoBinaryV_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> { defm "" : VPseudoBinaryV_VV<Constraint>; - defm "" : VPseudoBinaryV_VX</*IsFloat=*/false, Constraint>; + defm "" : VPseudoBinaryV_VX<Constraint>; defm "" : VPseudoBinaryV_VI<ImmType, Constraint>; } -multiclass VPseudoBinaryV_VV_VX<bit IsFloat = 0> { +multiclass VPseudoBinaryV_VV_VX { + defm "" : VPseudoBinaryV_VV; + defm "" : VPseudoBinaryV_VX; +} + +multiclass VPseudoBinaryV_VV_VF { defm "" : VPseudoBinaryV_VV; - defm "" : VPseudoBinaryV_VX<IsFloat>; + defm "" : VPseudoBinaryV_VF; } multiclass VPseudoBinaryV_VX_VI<Operand ImmType = simm5> { - defm "" : VPseudoBinaryV_VX</*IsFloat=*/0>; + defm "" : VPseudoBinaryV_VX; defm "" : VPseudoBinaryV_VI<ImmType>; } -multiclass VPseudoBinaryW_VV_VX<bit IsFloat = 0> { +multiclass VPseudoBinaryW_VV_VX { defm "" : VPseudoBinaryW_VV; - defm "" : VPseudoBinaryW_VX<IsFloat>; + defm "" : VPseudoBinaryW_VX; } -multiclass VPseudoBinaryW_WV_WX<bit IsFloat = 0> { +multiclass VPseudoBinaryW_VV_VF { + defm "" : VPseudoBinaryW_VV; + defm "" : VPseudoBinaryW_VF; +} + +multiclass VPseudoBinaryW_WV_WX { defm "" : VPseudoBinaryW_WV; - defm "" : VPseudoBinaryW_WX<IsFloat>; + defm "" : VPseudoBinaryW_WX; +} + +multiclass VPseudoBinaryW_WV_WF { + defm "" : VPseudoBinaryW_WV; + defm "" : VPseudoBinaryW_WF; } multiclass VPseudoBinaryV_VM_XM_IM { @@ -1655,10 +1723,16 @@ multiclass VPseudoTernaryV_VX<string Constraint = ""> { defm _VX : VPseudoTernary<m.vrclass, m.vrclass, GPR, m, Constraint>; } -multiclass VPseudoTernaryV_VX_AAXA<bit IsFloat, string Constraint = ""> { +multiclass VPseudoTernaryV_VX_AAXA<string Constraint = ""> { foreach m = MxList.m in - defm !if(IsFloat, "_VF", "_VX") : VPseudoTernary<m.vrclass, - !if(IsFloat, FPR32, GPR), m.vrclass, m, Constraint>; + defm "_VX" : VPseudoTernary<m.vrclass, GPR, m.vrclass, m, Constraint>; +} + +multiclass VPseudoTernaryV_VF_AAXA<string Constraint = ""> { + foreach m = MxList.m in + foreach f = FPList.fpinfo in + defm "_VF_" # f.FX : VPseudoTernary<m.vrclass, f.fprclass, m.vrclass, + m, Constraint>; } multiclass VPseudoTernaryW_VV { @@ -1667,11 +1741,18 @@ multiclass VPseudoTernaryW_VV { defm _VV : VPseudoTernary<m.wvrclass, m.vrclass, m.vrclass, m, constraint>; } -multiclass VPseudoTernaryW_VX<bit IsFloat> { +multiclass VPseudoTernaryW_VX { + defvar constraint = "@earlyclobber $rd"; + foreach m = MxList.m[0-5] in + defm "_VX" : VPseudoTernary<m.wvrclass, GPR, m.vrclass, m, constraint>; +} + +multiclass VPseudoTernaryW_VF { defvar constraint = "@earlyclobber $rd"; foreach m = MxList.m[0-5] in - defm !if(IsFloat, "_VF", "_VX") : VPseudoTernary<m.wvrclass, - !if(IsFloat, FPR32, GPR), m.vrclass, m, constraint>; + foreach f = FPList.fpinfo[0-1] in + defm "_VF_" # f.FX : VPseudoTernary<m.wvrclass, f.fprclass, m.vrclass, m, + constraint>; } multiclass VPseudoTernaryV_VI<Operand ImmType = simm5, string Constraint = ""> { @@ -1679,9 +1760,14 @@ multiclass VPseudoTernaryV_VI<Operand ImmType = simm5, string Constraint = ""> { defm _VI : VPseudoTernary<m.vrclass, m.vrclass, ImmType, m, Constraint>; } -multiclass VPseudoTernaryV_VV_VX_AAXA<bit IsFloat = 0, string Constraint = ""> { +multiclass VPseudoTernaryV_VV_VX_AAXA<string Constraint = ""> { + defm "" : VPseudoTernaryV_VV<Constraint>; + defm "" : VPseudoTernaryV_VX_AAXA<Constraint>; +} + +multiclass VPseudoTernaryV_VV_VF_AAXA<string Constraint = ""> { defm "" : VPseudoTernaryV_VV<Constraint>; - defm "" : VPseudoTernaryV_VX_AAXA<IsFloat, Constraint>; + defm "" : VPseudoTernaryV_VF_AAXA<Constraint>; } multiclass VPseudoTernaryV_VX_VI<Operand ImmType = simm5, string Constraint = ""> { @@ -1689,24 +1775,34 @@ multiclass VPseudoTernaryV_VX_VI<Operand ImmType = simm5, string Constraint = "" defm "" : VPseudoTernaryV_VI<ImmType, Constraint>; } -multiclass VPseudoTernaryW_VV_VX<bit IsFloat = false> { +multiclass VPseudoTernaryW_VV_VX { defm "" : VPseudoTernaryW_VV; - defm "" : VPseudoTernaryW_VX<IsFloat>; + defm "" : VPseudoTernaryW_VX; +} + +multiclass VPseudoTernaryW_VV_VF { + defm "" : VPseudoTernaryW_VV; + defm "" : VPseudoTernaryW_VF; } multiclass VPseudoBinaryM_VV_VX_VI { defm "" : VPseudoBinaryM_VV; - defm "" : VPseudoBinaryM_VX</*IsFloat=*/0>; + defm "" : VPseudoBinaryM_VX; defm "" : VPseudoBinaryM_VI; } -multiclass VPseudoBinaryM_VV_VX<bit IsFloat = 0> { +multiclass VPseudoBinaryM_VV_VX { + defm "" : VPseudoBinaryM_VV; + defm "" : VPseudoBinaryM_VX; +} + +multiclass VPseudoBinaryM_VV_VF { defm "" : VPseudoBinaryM_VV; - defm "" : VPseudoBinaryM_VX<IsFloat>; + defm "" : VPseudoBinaryM_VF; } multiclass VPseudoBinaryM_VX_VI { - defm "" : VPseudoBinaryM_VX</*IsFloat=*/0>; + defm "" : VPseudoBinaryM_VX; defm "" : VPseudoBinaryM_VI; } @@ -1947,7 +2043,7 @@ class VPatBinaryNoMask<string intrinsic_name, (XLenVT GPR:$vl))), (!cast<Instruction>(inst) (op1_type op1_reg_class:$rs1), - ToFPR32<op2_type, op2_kind, "rs2">.ret, + (op2_type op2_kind:$rs2), (NoX0 GPR:$vl), sew)>; class VPatBinaryMask<string intrinsic_name, @@ -1969,7 +2065,7 @@ class VPatBinaryMask<string intrinsic_name, (!cast<Instruction>(inst#"_MASK") (result_type result_reg_class:$merge), (op1_type op1_reg_class:$rs1), - ToFPR32<op2_type, op2_kind, "rs2">.ret, + (op2_type op2_kind:$rs2), (mask_type V0), (NoX0 GPR:$vl), sew)>; class VPatTernaryNoMask<string intrinsic, @@ -1989,9 +2085,9 @@ class VPatTernaryNoMask<string intrinsic, (op1_type op1_reg_class:$rs1), (op2_type op2_kind:$rs2), (XLenVT GPR:$vl))), - (!cast<Instruction>(inst#_#kind#"_"# vlmul.MX) + (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX) result_reg_class:$rs3, - ToFPR32<op1_type, op1_reg_class, "rs1">.ret, + (op1_type op1_reg_class:$rs1), op2_kind:$rs2, (NoX0 GPR:$vl), sew)>; @@ -2013,9 +2109,9 @@ class VPatTernaryMask<string intrinsic, (op2_type op2_kind:$rs2), (mask_type V0), (XLenVT GPR:$vl))), - (!cast<Instruction>(inst#_#kind#"_"# vlmul.MX # "_MASK") + (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX # "_MASK") result_reg_class:$rs3, - ToFPR32<op1_type, op1_reg_class, "rs1">.ret, + (op1_type op1_reg_class:$rs1), op2_kind:$rs2, (mask_type V0), (NoX0 GPR:$vl), sew)>; @@ -2330,7 +2426,7 @@ multiclass VPatBinaryCarryIn<string intrinsic, (XLenVT GPR:$vl))), (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX) (op1_type op1_reg_class:$rs1), - ToFPR32<op2_type, op2_kind, "rs2">.ret, + (op2_type op2_kind:$rs2), (mask_type V0), (NoX0 GPR:$vl), sew)>; } @@ -2351,7 +2447,7 @@ multiclass VPatBinaryMaskOut<string intrinsic, (XLenVT GPR:$vl))), (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX) (op1_type op1_reg_class:$rs1), - ToFPR32<op2_type, op2_kind, "rs2">.ret, + (op2_type op2_kind:$rs2), (NoX0 GPR:$vl), sew)>; } @@ -2414,8 +2510,8 @@ multiclass VPatBinaryV_VV_INT_EEW<string intrinsic, string instruction, multiclass VPatBinaryV_VX<string intrinsic, string instruction, list<VTypeInfo> vtilist> { foreach vti = vtilist in { - defvar kind = !if(!eq(vti.Scalar, XLenVT), "_VX_", "_VF_"); - defm : VPatBinary<intrinsic, instruction # kind # vti.LMul.MX, + defvar kind = getScalarSuffix<vti.Scalar>.suffix; + defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#vti.LMul.MX, vti.Vector, vti.Vector, vti.Scalar, vti.Mask, vti.SEW, vti.RegClass, vti.RegClass, vti.ScalarRegClass>; @@ -2464,8 +2560,8 @@ multiclass VPatBinaryW_VX<string intrinsic, string instruction, foreach VtiToWti = vtilist in { defvar Vti = VtiToWti.Vti; defvar Wti = VtiToWti.Wti; - defvar kind = !if(!eq(Vti.Scalar, XLenVT), "_VX_", "_VF_"); - defm : VPatBinary<intrinsic, instruction # kind # Vti.LMul.MX, + defvar kind = getScalarSuffix<Vti.Scalar>.suffix; + defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX, Wti.Vector, Vti.Vector, Vti.Scalar, Vti.Mask, Vti.SEW, Wti.RegClass, Vti.RegClass, Vti.ScalarRegClass>; @@ -2489,8 +2585,8 @@ multiclass VPatBinaryW_WX<string intrinsic, string instruction, foreach VtiToWti = vtilist in { defvar Vti = VtiToWti.Vti; defvar Wti = VtiToWti.Wti; - defvar kind = !if(!eq(Vti.Scalar, XLenVT), "_WX_", "_WF_"); - defm : VPatBinary<intrinsic, instruction # kind # Vti.LMul.MX, + defvar kind = getWScalarSuffix<Vti.Scalar>.suffix; + defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX, Wti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask, Vti.SEW, Wti.RegClass, Wti.RegClass, Vti.ScalarRegClass>; @@ -2514,8 +2610,8 @@ multiclass VPatBinaryV_WX<string intrinsic, string instruction, foreach VtiToWti = vtilist in { defvar Vti = VtiToWti.Vti; defvar Wti = VtiToWti.Wti; - defvar kind = !if(!eq(Vti.Scalar, XLenVT), "_WX_", "_WF_"); - defm : VPatBinary<intrinsic, instruction # kind # Vti.LMul.MX, + defvar kind = getWScalarSuffix<Vti.Scalar>.suffix; + defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX, Vti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask, Vti.SEW, Vti.RegClass, Wti.RegClass, Vti.ScalarRegClass>; @@ -2550,7 +2646,10 @@ multiclass VPatBinaryV_XM<string intrinsic, string instruction, list<VTypeInfo> vtilist = AllIntegerVectors> { foreach vti = vtilist in defm : VPatBinaryCarryIn<intrinsic, instruction, - !if(!eq(vti.Scalar, XLenVT), "VXM", "VFM"), + !cond(!eq(vti.Scalar, XLenVT): "VXM", + !eq(vti.Scalar, f16): "VFM_F16", + !eq(vti.Scalar, f32): "VFM_F32", + !eq(vti.Scalar, f64): "VFM_F64"), !if(CarryOut, vti.Mask, vti.Vector), vti.Vector, vti.Scalar, vti.Mask, vti.SEW, vti.LMul, @@ -2603,8 +2702,8 @@ multiclass VPatBinaryM_VV<string intrinsic, string instruction, multiclass VPatBinaryM_VX<string intrinsic, string instruction, list<VTypeInfo> vtilist> { foreach vti = vtilist in { - defvar kind = !if(!eq(vti.Scalar, XLenVT), "_VX_", "_VF_"); - defm : VPatBinary<intrinsic, instruction # kind # vti.LMul.MX, + defvar kind = getScalarSuffix<vti.Scalar>.suffix; + defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#vti.LMul.MX, vti.Mask, vti.Vector, vti.Scalar, vti.Mask, vti.SEW, VR, vti.RegClass, vti.ScalarRegClass>; @@ -2745,7 +2844,7 @@ multiclass VPatTernaryV_VX_AAXA<string intrinsic, string instruction, list<VTypeInfo> vtilist> { foreach vti = vtilist in defm : VPatTernary<intrinsic, instruction, - !if(!eq(vti.Scalar, XLenVT), "VX", "VF"), + getScalarSuffix<vti.Scalar>.suffix, vti.Vector, vti.Scalar, vti.Vector, vti.Mask, vti.SEW, vti.LMul, vti.RegClass, vti.ScalarRegClass, vti.RegClass>; @@ -2778,7 +2877,7 @@ multiclass VPatTernaryW_VX<string intrinsic, string instruction, defvar vti = vtiToWti.Vti; defvar wti = vtiToWti.Wti; defm : VPatTernary<intrinsic, instruction, - !if(!eq(vti.Scalar, XLenVT), "VX", "VF"), + getScalarSuffix<vti.Scalar>.suffix, wti.Vector, vti.Scalar, vti.Vector, vti.Mask, vti.SEW, vti.LMul, wti.RegClass, vti.ScalarRegClass, vti.RegClass>; @@ -3237,7 +3336,7 @@ defm PseudoVNMSUB : VPseudoTernaryV_VV_VX_AAXA; defm PseudoVWMACCU : VPseudoTernaryW_VV_VX; defm PseudoVWMACC : VPseudoTernaryW_VV_VX; defm PseudoVWMACCSU : VPseudoTernaryW_VV_VX; -defm PseudoVWMACCUS : VPseudoTernaryW_VX</*IsFloat*/false>; +defm PseudoVWMACCUS : VPseudoTernaryW_VX; //===----------------------------------------------------------------------===// // 12.16. Vector Integer Merge Instructions @@ -3298,49 +3397,49 @@ let Predicates = [HasStdExtV, HasStdExtF] in { //===----------------------------------------------------------------------===// // 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions //===----------------------------------------------------------------------===// -defm PseudoVFADD : VPseudoBinaryV_VV_VX</*IsFloat=*/1>; -defm PseudoVFSUB : VPseudoBinaryV_VV_VX</*IsFloat=*/1>; -defm PseudoVFRSUB : VPseudoBinaryV_VX</*IsFloat=*/1>; +defm PseudoVFADD : VPseudoBinaryV_VV_VF; +defm PseudoVFSUB : VPseudoBinaryV_VV_VF; +defm PseudoVFRSUB : VPseudoBinaryV_VF; //===----------------------------------------------------------------------===// // 14.3. Vector Widening Floating-Point Add/Subtract Instructions //===----------------------------------------------------------------------===// -defm PseudoVFWADD : VPseudoBinaryW_VV_VX</*IsFloat=*/1>; -defm PseudoVFWSUB : VPseudoBinaryW_VV_VX</*IsFloat=*/1>; -defm PseudoVFWADD : VPseudoBinaryW_WV_WX</*IsFloat=*/1>; -defm PseudoVFWSUB : VPseudoBinaryW_WV_WX</*IsFloat=*/1>; +defm PseudoVFWADD : VPseudoBinaryW_VV_VF; +defm PseudoVFWSUB : VPseudoBinaryW_VV_VF; +defm PseudoVFWADD : VPseudoBinaryW_WV_WF; +defm PseudoVFWSUB : VPseudoBinaryW_WV_WF; //===----------------------------------------------------------------------===// // 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions //===----------------------------------------------------------------------===// -defm PseudoVFMUL : VPseudoBinaryV_VV_VX</*IsFloat=*/1>; -defm PseudoVFDIV : VPseudoBinaryV_VV_VX</*IsFloat=*/1>; -defm PseudoVFRDIV : VPseudoBinaryV_VX</*IsFloat=*/1>; +defm PseudoVFMUL : VPseudoBinaryV_VV_VF; +defm PseudoVFDIV : VPseudoBinaryV_VV_VF; +defm PseudoVFRDIV : VPseudoBinaryV_VF; //===----------------------------------------------------------------------===// // 14.5. Vector Widening Floating-Point Multiply //===----------------------------------------------------------------------===// -defm PseudoVFWMUL : VPseudoBinaryW_VV_VX</*IsFloat=*/1>; +defm PseudoVFWMUL : VPseudoBinaryW_VV_VF; //===----------------------------------------------------------------------===// // 14.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions //===----------------------------------------------------------------------===// -defm PseudoVFMACC : VPseudoTernaryV_VV_VX_AAXA</*IsFloat*/true>; -defm PseudoVFNMACC : VPseudoTernaryV_VV_VX_AAXA</*IsFloat*/true>; -defm PseudoVFMSAC : VPseudoTernaryV_VV_VX_AAXA</*IsFloat*/true>; -defm PseudoVFNMSAC : VPseudoTernaryV_VV_VX_AAXA</*IsFloat*/true>; -defm PseudoVFMADD : VPseudoTernaryV_VV_VX_AAXA</*IsFloat*/true>; -defm PseudoVFNMADD : VPseudoTernaryV_VV_VX_AAXA</*IsFloat*/true>; -defm PseudoVFMSUB : VPseudoTernaryV_VV_VX_AAXA</*IsFloat*/true>; -defm PseudoVFNMSUB : VPseudoTernaryV_VV_VX_AAXA</*IsFloat*/true>; +defm PseudoVFMACC : VPseudoTernaryV_VV_VF_AAXA; +defm PseudoVFNMACC : VPseudoTernaryV_VV_VF_AAXA; +defm PseudoVFMSAC : VPseudoTernaryV_VV_VF_AAXA; +defm PseudoVFNMSAC : VPseudoTernaryV_VV_VF_AAXA; +defm PseudoVFMADD : VPseudoTernaryV_VV_VF_AAXA; +defm PseudoVFNMADD : VPseudoTernaryV_VV_VF_AAXA; +defm PseudoVFMSUB : VPseudoTernaryV_VV_VF_AAXA; +defm PseudoVFNMSUB : VPseudoTernaryV_VV_VF_AAXA; //===----------------------------------------------------------------------===// // 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions //===----------------------------------------------------------------------===// -defm PseudoVFWMACC : VPseudoTernaryW_VV_VX</*IsFloat*/true>; -defm PseudoVFWNMACC : VPseudoTernaryW_VV_VX</*IsFloat*/true>; -defm PseudoVFWMSAC : VPseudoTernaryW_VV_VX</*IsFloat*/true>; -defm PseudoVFWNMSAC : VPseudoTernaryW_VV_VX</*IsFloat*/true>; +defm PseudoVFWMACC : VPseudoTernaryW_VV_VF; +defm PseudoVFWNMACC : VPseudoTernaryW_VV_VF; +defm PseudoVFWMSAC : VPseudoTernaryW_VV_VF; +defm PseudoVFWNMSAC : VPseudoTernaryW_VV_VF; //===----------------------------------------------------------------------===// // 14.8. Vector Floating-Point Square-Root Instruction @@ -3360,25 +3459,25 @@ defm PseudoVFRECE7 : VPseudoUnaryV_V; //===----------------------------------------------------------------------===// // 14.11. Vector Floating-Point Min/Max Instructions //===----------------------------------------------------------------------===// -defm PseudoVFMIN : VPseudoBinaryV_VV_VX</*IsFloat=*/1>; -defm PseudoVFMAX : VPseudoBinaryV_VV_VX</*IsFloat=*/1>; +defm PseudoVFMIN : VPseudoBinaryV_VV_VF; +defm PseudoVFMAX : VPseudoBinaryV_VV_VF; //===----------------------------------------------------------------------===// // 14.12. Vector Floating-Point Sign-Injection Instructions //===----------------------------------------------------------------------===// -defm PseudoVFSGNJ : VPseudoBinaryV_VV_VX</*IsFloat=*/1>; -defm PseudoVFSGNJN : VPseudoBinaryV_VV_VX</*IsFloat=*/1>; -defm PseudoVFSGNJX : VPseudoBinaryV_VV_VX</*IsFloat=*/1>; +defm PseudoVFSGNJ : VPseudoBinaryV_VV_VF; +defm PseudoVFSGNJN : VPseudoBinaryV_VV_VF; +defm PseudoVFSGNJX : VPseudoBinaryV_VV_VF; //===----------------------------------------------------------------------===// // 14.13. Vector Floating-Point Compare Instructions //===----------------------------------------------------------------------===// -defm PseudoVMFEQ : VPseudoBinaryM_VV_VX</*IsFloat=*/1>; -defm PseudoVMFNE : VPseudoBinaryM_VV_VX</*IsFloat=*/1>; -defm PseudoVMFLT : VPseudoBinaryM_VV_VX</*IsFloat=*/1>; -defm PseudoVMFLE : VPseudoBinaryM_VV_VX</*IsFloat=*/1>; -defm PseudoVMFGT : VPseudoBinaryM_VX</*IsFloat=*/1>; -defm PseudoVMFGE : VPseudoBinaryM_VX</*IsFloat=*/1>; +defm PseudoVMFEQ : VPseudoBinaryM_VV_VF; +defm PseudoVMFNE : VPseudoBinaryM_VV_VF; +defm PseudoVMFLT : VPseudoBinaryM_VV_VF; +defm PseudoVMFLE : VPseudoBinaryM_VV_VF; +defm PseudoVMFGT : VPseudoBinaryM_VF; +defm PseudoVMFGE : VPseudoBinaryM_VF; //===----------------------------------------------------------------------===// // 14.14. Vector Floating-Point Classify Instruction @@ -3388,8 +3487,7 @@ defm PseudoVFCLASS : VPseudoUnaryV_V; //===----------------------------------------------------------------------===// // 14.15. Vector Floating-Point Merge Instruction //===----------------------------------------------------------------------===// -defm PseudoVFMERGE : VPseudoBinaryV_XM</*CarryOut =*/0,/*CarryIn =*/true, - /*Constraint =*/"", /*IsFloat=*/true>; +defm PseudoVFMERGE : VPseudoBinaryV_FM; //===----------------------------------------------------------------------===// // 14.16. Vector Floating-Point Move Instruction @@ -3561,18 +3659,22 @@ let Predicates = [HasStdExtV, HasStdExtF] in { let mayLoad = 0, mayStore = 0, hasSideEffects = 0, usesCustomInserter = 1, Uses = [VL, VTYPE] in { foreach m = MxList.m in { - let VLMul = m.value in { - let HasSEWOp = 1, BaseInstr = VFMV_F_S in - def PseudoVFMV_F_S # "_" # m.MX : Pseudo<(outs FPR32:$rd), - (ins m.vrclass:$rs2, - ixlenimm:$sew), - []>, RISCVVPseudo; - let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F, WritesElement0 = 1, - Constraints = "$rd = $rs1" in - def PseudoVFMV_S_F # "_" # m.MX : Pseudo<(outs m.vrclass:$rd), - (ins m.vrclass:$rs1, FPR32:$rs2, - GPR:$vl, ixlenimm:$sew), - []>, RISCVVPseudo; + foreach f = FPList.fpinfo in { + let VLMul = m.value in { + let HasSEWOp = 1, BaseInstr = VFMV_F_S in + def PseudoVFMV_F_S # "_" # f.FX # "_" # m.MX : + Pseudo<(outs f.fprclass:$rd), + (ins m.vrclass:$rs2, + ixlenimm:$sew), + []>, RISCVVPseudo; + let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F, WritesElement0 = 1, + Constraints = "$rd = $rs1" in + def PseudoVFMV_S_F # "_" # f.FX #"_" # m.MX : + Pseudo<(outs m.vrclass:$rd), + (ins m.vrclass:$rs1, f.fprclass:$rs2, + GPR:$vl, ixlenimm:$sew), + []>, RISCVVPseudo; + } } } } @@ -3584,13 +3686,13 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0, usesCustomInserter = 1, let Predicates = [HasStdExtV] in { defm PseudoVSLIDEUP : VPseudoTernaryV_VX_VI<uimm5, "@earlyclobber $rd">; defm PseudoVSLIDEDOWN : VPseudoTernaryV_VX_VI<uimm5>; - defm PseudoVSLIDE1UP : VPseudoBinaryV_VX</*IsFloat*/false, "@earlyclobber $rd">; - defm PseudoVSLIDE1DOWN : VPseudoBinaryV_VX</*IsFloat*/false>; + defm PseudoVSLIDE1UP : VPseudoBinaryV_VX<"@earlyclobber $rd">; + defm PseudoVSLIDE1DOWN : VPseudoBinaryV_VX; } // Predicates = [HasStdExtV] let Predicates = [HasStdExtV, HasStdExtF] in { - defm PseudoVFSLIDE1UP : VPseudoBinaryV_VX</*IsFloat*/true, "@earlyclobber $rd">; - defm PseudoVFSLIDE1DOWN : VPseudoBinaryV_VX</*IsFloat*/true>; + defm PseudoVFSLIDE1UP : VPseudoBinaryV_VF<"@earlyclobber $rd">; + defm PseudoVFSLIDE1DOWN : VPseudoBinaryV_VF; } // Predicates = [HasStdExtV, HasStdExtF] //===----------------------------------------------------------------------===// @@ -4083,8 +4185,12 @@ foreach fvti = AllFloatVectors in { def : Pat<(fvti.Vector (int_riscv_vfmv_v_f (fvti.Scalar fvti.ScalarRegClass:$rs2), GPR:$vl)), - (!cast<Instruction>("PseudoVFMV_V_F_"#fvti.LMul.MX) - ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs2">.ret, + (!cast<Instruction>("PseudoVFMV_V_F_" # + !cond(!eq(fvti.Scalar, f16): "F16_", + !eq(fvti.Scalar, f32): "F32_", + !eq(fvti.Scalar, f64): "F64_") # + fvti.LMul.MX) + (fvti.Scalar fvti.ScalarRegClass:$rs2), (NoX0 GPR:$vl), fvti.SEW)>; } @@ -4242,27 +4348,23 @@ foreach vti = AllIntegerVectors in { let Predicates = [HasStdExtV, HasStdExtF] in { foreach fvti = AllFloatVectors in { - defvar instr = !cast<Instruction>("PseudoVFMV_F_S_" # fvti.LMul.MX); + defvar instr = !cast<Instruction>("PseudoVFMV_F_S_" # + !cond(!eq(fvti.Scalar, f16): "F16_", + !eq(fvti.Scalar, f32): "F32_", + !eq(fvti.Scalar, f64): "F64_") # + fvti.LMul.MX); def : Pat<(fvti.Scalar (int_riscv_vfmv_f_s (fvti.Vector fvti.RegClass:$rs2))), - // Floating point instructions with a scalar result will always - // generate the result in a register of class FPR32. When dealing - // with the f64 variant of a pattern we need to promote the FPR32 - // subregister generated by the instruction to the FPR64 base - // register expected by the type in the pattern - !cond(!eq(!cast<string>(fvti.ScalarRegClass), - !cast<string>(FPR64)): - (SUBREG_TO_REG (i32 -1), - (instr $rs2, fvti.SEW), sub_32), - !eq(!cast<string>(fvti.ScalarRegClass), - !cast<string>(FPR16)): - (EXTRACT_SUBREG (instr $rs2, fvti.SEW), sub_16), - !eq(1, 1): - (instr $rs2, fvti.SEW))>; + (instr $rs2, fvti.SEW)>; def : Pat<(fvti.Vector (int_riscv_vfmv_s_f (fvti.Vector fvti.RegClass:$rs1), (fvti.Scalar fvti.ScalarRegClass:$rs2), GPR:$vl)), - (!cast<Instruction>("PseudoVFMV_S_F_" # fvti.LMul.MX) - (fvti.Vector $rs1), ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs2">.ret, + (!cast<Instruction>("PseudoVFMV_S_F_" # + !cond(!eq(fvti.Scalar, f16): "F16_", + !eq(fvti.Scalar, f32): "F32_", + !eq(fvti.Scalar, f64): "F64_") # + fvti.LMul.MX) + (fvti.Vector $rs1), + (fvti.Scalar fvti.ScalarRegClass:$rs2), (NoX0 GPR:$vl), fvti.SEW)>; } } // Predicates = [HasStdExtV, HasStdExtF] diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td index 95f57ae..23792dc 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td @@ -48,6 +48,18 @@ def SplatPat : ComplexPattern<vAny, 1, "selectVSplat", [], [], 1>; def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", []>; def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", []>; +// FIXME: We only model FPR32 for V instructions in RISCVInstrInfoV.td. +// FP16/FP32/FP64 registers are alias each other. Convert FPR16 and FPR64 +// to FPR32 for V instructions is enough. +class ToFPR32<ValueType type, DAGOperand operand, string name> { + dag ret = !cond(!eq(!cast<string>(operand), !cast<string>(FPR64)): + (EXTRACT_SUBREG !dag(type, [FPR64], [name]), sub_32), + !eq(!cast<string>(operand), !cast<string>(FPR16)): + (SUBREG_TO_REG (i16 -1), !dag(type, [FPR16], [name]), sub_16), + !eq(1, 1): + !dag(type, [operand], [name])); +} + class SwapHelper<dag Prefix, dag A, dag B, dag Suffix, bit swap> { dag Value = !con(Prefix, !if(swap, B, A), !if(swap, A, B), Suffix); } @@ -162,7 +174,7 @@ class VPatBinarySDNode_VF<SDNode vop, DAGOperand xop_kind> : Pat<(result_type (vop (vop_type vop_reg_class:$rs1), (vop_type (splat_vector xop_kind:$rs2)))), - (!cast<Instruction>(instruction_name#"_VF_"#vlmul.MX) + (!cast<Instruction>(instruction_name#"_VF_F32_"#vlmul.MX) vop_reg_class:$rs1, ToFPR32<xop_type, xop_kind, "rs2">.ret, avl, sew)>; @@ -183,7 +195,7 @@ multiclass VPatBinaryFPSDNode_R_VF<SDNode vop, string instruction_name> { foreach fvti = AllFloatVectors in def : Pat<(fvti.Vector (vop (fvti.Vector (splat_vector fvti.Scalar:$rs2)), (fvti.Vector fvti.RegClass:$rs1))), - (!cast<Instruction>(instruction_name#"_VF_"#fvti.LMul.MX) + (!cast<Instruction>(instruction_name#"_VF_F32_"#fvti.LMul.MX) fvti.RegClass:$rs1, ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs2">.ret, fvti.AVL, fvti.SEW)>; @@ -263,7 +275,7 @@ multiclass VPatFPSetCCSDNode_VF<CondCode cc, string instruction_name> { def : Pat<(fvti.Mask (setcc (fvti.Vector fvti.RegClass:$rs1), (fvti.Vector (splat_vector fvti.ScalarRegClass:$rs2)), cc)), - (!cast<Instruction>(instruction_name#"_VF_"#fvti.LMul.MX) + (!cast<Instruction>(instruction_name#"_VF_F32_"#fvti.LMul.MX) fvti.RegClass:$rs1, ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs2">.ret, fvti.AVL, fvti.SEW)>; @@ -274,7 +286,7 @@ multiclass VPatFPSetCCSDNode_FV<CondCode cc, string swapped_op_instruction_name> def : Pat<(fvti.Mask (setcc (fvti.Vector (splat_vector fvti.ScalarRegClass:$rs2)), (fvti.Vector fvti.RegClass:$rs1), cc)), - (!cast<Instruction>(swapped_op_instruction_name#"_VF_"#fvti.LMul.MX) + (!cast<Instruction>(swapped_op_instruction_name#"_VF_F32_"#fvti.LMul.MX) fvti.RegClass:$rs1, ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs2">.ret, fvti.AVL, fvti.SEW)>; @@ -487,7 +499,7 @@ foreach fvti = AllFloatVectors in { def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm), (splat_vector fvti.ScalarRegClass:$rs1), fvti.RegClass:$rs2)), - (!cast<Instruction>("PseudoVFMERGE_VFM_"#fvti.LMul.MX) + (!cast<Instruction>("PseudoVFMERGE_VFM_F32_"#fvti.LMul.MX) fvti.RegClass:$rs2, ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs1">.ret, VMV0:$vm, fvti.AVL, fvti.SEW)>; @@ -538,7 +550,7 @@ foreach vti = AllIntegerVectors in { let Predicates = [HasStdExtV, HasStdExtF] in { foreach fvti = AllFloatVectors in { def : Pat<(fvti.Vector (splat_vector fvti.ScalarRegClass:$rs1)), - (!cast<Instruction>("PseudoVFMV_V_F_"#fvti.LMul.MX) + (!cast<Instruction>("PseudoVFMV_V_F_F32_"#fvti.LMul.MX) ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs1">.ret, fvti.AVL, fvti.SEW)>; @@ -570,9 +582,9 @@ multiclass VPatInsertExtractElt_XI_Idx<bit IsFloat> { defvar extractelt_node = !if(IsFloat, extractelt, riscv_extract_vector_elt); foreach vti = vtilist in { defvar MX = vti.LMul.MX; - defvar vmv_xf_s_inst = !cast<Instruction>(!if(IsFloat, "PseudoVFMV_F_S_", + defvar vmv_xf_s_inst = !cast<Instruction>(!if(IsFloat, "PseudoVFMV_F_S_F32_", "PseudoVMV_X_S_")#MX); - defvar vmv_s_xf_inst = !cast<Instruction>(!if(IsFloat, "PseudoVFMV_S_F_", + defvar vmv_s_xf_inst = !cast<Instruction>(!if(IsFloat, "PseudoVFMV_S_F_F32_", "PseudoVMV_S_X_")#MX); // Only pattern-match insert/extract-element operations where the index is // 0. Any other index will have been custom-lowered to slide the vector diff --git a/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp b/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp index 5051034..3c38dd1 100644 --- a/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp +++ b/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp @@ -178,6 +178,12 @@ static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI, RISCV::VRM8RegClass.contains(Reg)) { Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0); assert(Reg && "Subregister does not exist"); + } else if (RISCV::FPR16RegClass.contains(Reg)) { + Reg = TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass); + assert(Reg && "Subregister does not exist"); + } else if (RISCV::FPR64RegClass.contains(Reg)) { + Reg = TRI->getSubReg(Reg, RISCV::sub_32); + assert(Reg && "Superregister does not exist"); } MCOp = MCOperand::createReg(Reg); diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll b/llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll index 76004c0..10e6051 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll @@ -9,7 +9,6 @@ define half @intrinsic_vfmv.f.s_s_nxv1f16(<vscale x 1 x half> %0) nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu ; CHECK-NEXT: vfmv.f.s fa0, v8 -; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f ; CHECK-NEXT: ret entry: %a = call half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half> %0) @@ -23,7 +22,6 @@ define half @intrinsic_vfmv.f.s_s_nxv2f16(<vscale x 2 x half> %0) nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu ; CHECK-NEXT: vfmv.f.s fa0, v8 -; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f ; CHECK-NEXT: ret entry: %a = call half @llvm.riscv.vfmv.f.s.nxv2f16(<vscale x 2 x half> %0) @@ -37,7 +35,6 @@ define half @intrinsic_vfmv.f.s_s_nxv4f16(<vscale x 4 x half> %0) nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu ; CHECK-NEXT: vfmv.f.s fa0, v8 -; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f ; CHECK-NEXT: ret entry: %a = call half @llvm.riscv.vfmv.f.s.nxv4f16(<vscale x 4 x half> %0) @@ -51,7 +48,6 @@ define half @intrinsic_vfmv.f.s_s_nxv8f16(<vscale x 8 x half> %0) nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,m2,ta,mu ; CHECK-NEXT: vfmv.f.s fa0, v8 -; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f ; CHECK-NEXT: ret entry: %a = call half @llvm.riscv.vfmv.f.s.nxv8f16(<vscale x 8 x half> %0) @@ -65,7 +61,6 @@ define half @intrinsic_vfmv.f.s_s_nxv16f16(<vscale x 16 x half> %0) nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,m4,ta,mu ; CHECK-NEXT: vfmv.f.s fa0, v8 -; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f ; CHECK-NEXT: ret entry: %a = call half @llvm.riscv.vfmv.f.s.nxv16f16(<vscale x 16 x half> %0) @@ -79,7 +74,6 @@ define half @intrinsic_vfmv.f.s_s_nxv32f16(<vscale x 32 x half> %0) nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,m8,ta,mu ; CHECK-NEXT: vfmv.f.s fa0, v8 -; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f ; CHECK-NEXT: ret entry: %a = call half @llvm.riscv.vfmv.f.s.nxv32f16(<vscale x 32 x half> %0) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll index c1b7f54..3f1cd43 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll @@ -6,7 +6,6 @@ declare <vscale x 1 x half> @llvm.riscv.vfmv.s.f.nxv1f16(<vscale x 1 x half>, ha define <vscale x 1 x half> @intrinsic_vfmv.s.f_f_nxv1f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu ; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret @@ -20,7 +19,6 @@ declare <vscale x 2 x half> @llvm.riscv.vfmv.s.f.nxv2f16(<vscale x 2 x half>, ha define <vscale x 2 x half> @intrinsic_vfmv.s.f_f_nxv2f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu ; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret @@ -34,7 +32,6 @@ declare <vscale x 4 x half> @llvm.riscv.vfmv.s.f.nxv4f16(<vscale x 4 x half>, ha define <vscale x 4 x half> @intrinsic_vfmv.s.f_f_nxv4f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu ; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret @@ -48,7 +45,6 @@ declare <vscale x 8 x half> @llvm.riscv.vfmv.s.f.nxv8f16(<vscale x 8 x half>, ha define <vscale x 8 x half> @intrinsic_vfmv.s.f_f_nxv8f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu ; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret @@ -62,7 +58,6 @@ declare <vscale x 16 x half> @llvm.riscv.vfmv.s.f.nxv16f16(<vscale x 16 x half>, define <vscale x 16 x half> @intrinsic_vfmv.s.f_f_nxv16f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu ; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret @@ -76,7 +71,6 @@ declare <vscale x 32 x half> @llvm.riscv.vfmv.s.f.nxv32f16(<vscale x 32 x half>, define <vscale x 32 x half> @intrinsic_vfmv.s.f_f_nxv32f16(<vscale x 32 x half> %0, half %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu ; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll index f7db2bc..042c9b5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll @@ -6,7 +6,6 @@ declare <vscale x 1 x half> @llvm.riscv.vfmv.s.f.nxv1f16(<vscale x 1 x half>, ha define <vscale x 1 x half> @intrinsic_vfmv.s.f_f_nxv1f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu ; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret @@ -20,7 +19,6 @@ declare <vscale x 2 x half> @llvm.riscv.vfmv.s.f.nxv2f16(<vscale x 2 x half>, ha define <vscale x 2 x half> @intrinsic_vfmv.s.f_f_nxv2f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu ; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret @@ -34,7 +32,6 @@ declare <vscale x 4 x half> @llvm.riscv.vfmv.s.f.nxv4f16(<vscale x 4 x half>, ha define <vscale x 4 x half> @intrinsic_vfmv.s.f_f_nxv4f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu ; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret @@ -48,7 +45,6 @@ declare <vscale x 8 x half> @llvm.riscv.vfmv.s.f.nxv8f16(<vscale x 8 x half>, ha define <vscale x 8 x half> @intrinsic_vfmv.s.f_f_nxv8f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu ; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret @@ -62,7 +58,6 @@ declare <vscale x 16 x half> @llvm.riscv.vfmv.s.f.nxv16f16(<vscale x 16 x half>, define <vscale x 16 x half> @intrinsic_vfmv.s.f_f_nxv16f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu ; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret @@ -76,7 +71,6 @@ declare <vscale x 32 x half> @llvm.riscv.vfmv.s.f.nxv32f16(<vscale x 32 x half>, define <vscale x 32 x half> @intrinsic_vfmv.s.f_f_nxv32f16(<vscale x 32 x half> %0, half %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu ; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll index cfc0c51..c6567d2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll @@ -8,7 +8,6 @@ declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16( define <vscale x 1 x half> @intrinsic_vfmv.v.f_f_nxv1f16(half %0, i32 %1) nounwind { ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu ; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: jalr zero, 0(ra) @@ -27,7 +26,6 @@ declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16( define <vscale x 2 x half> @intrinsic_vfmv.v.f_f_nxv2f16(half %0, i32 %1) nounwind { ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu ; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: jalr zero, 0(ra) @@ -46,7 +44,6 @@ declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16( define <vscale x 4 x half> @intrinsic_vfmv.v.f_f_nxv4f16(half %0, i32 %1) nounwind { ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu ; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: jalr zero, 0(ra) @@ -65,7 +62,6 @@ declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16( define <vscale x 8 x half> @intrinsic_vfmv.v.f_f_nxv8f16(half %0, i32 %1) nounwind { ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu ; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: jalr zero, 0(ra) @@ -84,7 +80,6 @@ declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16( define <vscale x 16 x half> @intrinsic_vfmv.v.f_f_nxv16f16(half %0, i32 %1) nounwind { ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu ; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: jalr zero, 0(ra) @@ -103,7 +98,6 @@ declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16( define <vscale x 32 x half> @intrinsic_vfmv.v.f_f_nxv32f16(half %0, i32 %1) nounwind { ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu ; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: jalr zero, 0(ra) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll index c29f37f..19df844 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll @@ -8,7 +8,6 @@ declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16( define <vscale x 1 x half> @intrinsic_vfmv.v.f_f_nxv1f16(half %0, i64 %1) nounwind { ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu ; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: jalr zero, 0(ra) @@ -27,7 +26,6 @@ declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16( define <vscale x 2 x half> @intrinsic_vfmv.v.f_f_nxv2f16(half %0, i64 %1) nounwind { ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu ; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: jalr zero, 0(ra) @@ -46,7 +44,6 @@ declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16( define <vscale x 4 x half> @intrinsic_vfmv.v.f_f_nxv4f16(half %0, i64 %1) nounwind { ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu ; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: jalr zero, 0(ra) @@ -65,7 +62,6 @@ declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16( define <vscale x 8 x half> @intrinsic_vfmv.v.f_f_nxv8f16(half %0, i64 %1) nounwind { ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu ; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: jalr zero, 0(ra) @@ -84,7 +80,6 @@ declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16( define <vscale x 16 x half> @intrinsic_vfmv.v.f_f_nxv16f16(half %0, i64 %1) nounwind { ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu ; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: jalr zero, 0(ra) @@ -103,7 +98,6 @@ declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16( define <vscale x 32 x half> @intrinsic_vfmv.v.f_f_nxv32f16(half %0, i64 %1) nounwind { ; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu ; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: jalr zero, 0(ra) |