diff options
| -rw-r--r-- | llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/insn.s | 35 |
2 files changed, 32 insertions, 9 deletions
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp index 66970ed..54f1a38 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp @@ -77,7 +77,7 @@ public: /// Return binary encoding of operand. If the machine operand requires /// relocation, record the relocation and return zero. - unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, + uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const; @@ -375,7 +375,7 @@ void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, ++MCNumEmitted; // Keep track of the # of mi's emitted. } -unsigned +uint64_t RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const { @@ -384,7 +384,7 @@ RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); if (MO.isImm()) - return static_cast<unsigned>(MO.getImm()); + return MO.getImm(); llvm_unreachable("Unhandled expression!"); return 0; diff --git a/llvm/test/MC/RISCV/insn.s b/llvm/test/MC/RISCV/insn.s index e32fec2..d24f4fe 100644 --- a/llvm/test/MC/RISCV/insn.s +++ b/llvm/test/MC/RISCV/insn.s @@ -170,17 +170,40 @@ target: # CHECK-OBJ: <unknown> .insn 6, 0x1f -# CHECK-ASM: .insn 0x4, 65503 -# CHECK-ASM: encoding: [0xdf,0xff,0x00,0x00] -# CHECK-OBJ: <unknown> -.insn 0xffdf - # CHECK-ASM: .insn 0x8, 63 # CHECK-ASM: encoding: [0x3f,0x00,0x00,0x00,0x00,0x00,0x00,0x00] # CHECK-OBJ: <unknown> .insn 8, 0x3f +# CHECK-ASM: .insn 0x6, 281474976710623 +# CHECK-ASM: encoding: [0xdf,0xff,0xff,0xff,0xff,0xff] +# CHECK-OBJ: <unknown> +.insn 0x6, 0xffffffffffdf + +# CHECK-ASM: .insn 0x8, -65 +# CHECK-ASM: encoding: [0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff] +# CHECK-OBJ: <unknown> +.insn 0x8, 0xffffffffffffffbf + +odd_lengths: +# CHECK-ASM-LABEL: odd_lengths: +# CHECK-OBJ-LABEL: <odd_lengths>: + +## These deliberately disagree with the lengths objdump expects them to have, so +## keep them at the end so that the disassembled instruction stream is not out +## of sync with the encoded instruction stream. We don't check for `<unknown>` +## as we could get any number of those, so instead check for the encoding +## halfwords. These might be split into odd 16-bit chunks, so each chunk is on +## one line. + +# CHECK-ASM: .insn 0x4, 65503 +# CHECK-ASM: encoding: [0xdf,0xff,0x00,0x00] +# CHECK-OBJ: ffdf +# CHECK-OBJ: 0000 +.insn 0xffdf + # CHECK-ASM: .insn 0x4, 65471 # CHECK-ASM: encoding: [0xbf,0xff,0x00,0x00] -# CHECK-OBJ: <unknown> +# CHECK-OBJ: ffbf +# CHECK-OBJ: 0000 .insn 0xffbf |