diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 81fdfa0..c7abc58 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -10862,7 +10862,7 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N, /// Helper function for adjustWritemask static unsigned SubIdx2Lane(unsigned Idx) { switch (Idx) { - default: return 0; + default: return ~0u; case AMDGPU::sub0: return 0; case AMDGPU::sub1: return 1; case AMDGPU::sub2: return 2; @@ -10922,6 +10922,8 @@ SDNode *SITargetLowering::adjustWritemask(MachineSDNode *&Node, // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit // set, etc. Lane = SubIdx2Lane(I->getConstantOperandVal(1)); + if (Lane == ~0u) + return Node; // Check if the use is for the TFE/LWE generated result at VGPRn+1. if (UsesTFC && Lane == TFCLane) { |