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-rw-r--r--llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp29
-rw-r--r--llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll133
2 files changed, 157 insertions, 5 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
index c08549a..a6f74f3 100644
--- a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
@@ -193,7 +193,7 @@ static bool isSignExtendedW(Register SrcReg, MachineRegisterInfo &MRI,
case RISCV::REM:
case RISCV::ANDI:
case RISCV::ORI:
- case RISCV::XORI: {
+ case RISCV::XORI:
// |Remainder| is always <= |Dividend|. If D is 32-bit, then so is R.
// DIV doesn't work because of the edge case 0xf..f 8000 0000 / (long)-1
// Logical operations use a sign extended 12-bit immediate.
@@ -201,7 +201,13 @@ static bool isSignExtendedW(Register SrcReg, MachineRegisterInfo &MRI,
return false;
break;
- }
+ case RISCV::PseudoCCADDW:
+ case RISCV::PseudoCCSUBW:
+ // Returns operand 4 or an ADDW/SUBW of operands 5 and 6. We only need to
+ // check if operand 4 is sign extended.
+ if (!AddRegDefToWorkList(MI->getOperand(4).getReg()))
+ return false;
+ break;
case RISCV::REMU:
case RISCV::AND:
case RISCV::OR:
@@ -214,21 +220,34 @@ static bool isSignExtendedW(Register SrcReg, MachineRegisterInfo &MRI,
case RISCV::MIN:
case RISCV::MINU:
case RISCV::PseudoCCMOVGPR:
+ case RISCV::PseudoCCAND:
+ case RISCV::PseudoCCOR:
+ case RISCV::PseudoCCXOR:
case RISCV::PHI: {
// If all incoming values are sign-extended, the output of AND, OR, XOR,
// MIN, MAX, or PHI is also sign-extended.
// The input registers for PHI are operand 1, 3, ...
// The input registers for PseudoCCMOVGPR are 4 and 5.
+ // The input registers for PseudoCCAND/OR/XOR are 4, 5, and 6.
// The input registers for others are operand 1 and 2.
unsigned B = 1, E = 3, D = 1;
- if (MI->getOpcode() == RISCV::PHI) {
+ switch (MI->getOpcode()) {
+ case RISCV::PHI:
E = MI->getNumOperands();
D = 2;
- } else if (MI->getOpcode() == RISCV::PseudoCCMOVGPR) {
+ break;
+ case RISCV::PseudoCCMOVGPR:
B = 4;
E = 6;
- }
+ break;
+ case RISCV::PseudoCCAND:
+ case RISCV::PseudoCCOR:
+ case RISCV::PseudoCCXOR:
+ B = 4;
+ E = 7;
+ break;
+ }
for (unsigned I = B; I != E; I += D) {
if (!MI->getOperand(I).isReg())
diff --git a/llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll b/llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll
index 1f7b886..c239acc 100644
--- a/llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll
+++ b/llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll
@@ -377,3 +377,136 @@ entry:
%1 = select i1 %cmp10, i32 %A, i32 %0
ret i32 %1
}
+
+define void @sextw_removal_ccor(i1 %c, i32 signext %arg, i32 signext %arg1, i32 signext %arg2) nounwind {
+; NOSFB-LABEL: sextw_removal_ccor:
+; NOSFB: # %bb.0: # %bb
+; NOSFB-NEXT: addi sp, sp, -32
+; NOSFB-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; NOSFB-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; NOSFB-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; NOSFB-NEXT: mv s0, a2
+; NOSFB-NEXT: slli a0, a0, 63
+; NOSFB-NEXT: srai a0, a0, 63
+; NOSFB-NEXT: and a0, a0, a1
+; NOSFB-NEXT: or s1, a0, a3
+; NOSFB-NEXT: .LBB15_1: # %bb2
+; NOSFB-NEXT: # =>This Inner Loop Header: Depth=1
+; NOSFB-NEXT: mv a0, s1
+; NOSFB-NEXT: call bar@plt
+; NOSFB-NEXT: sllw s1, s1, s0
+; NOSFB-NEXT: bnez a0, .LBB15_1
+; NOSFB-NEXT: # %bb.2: # %bb7
+; NOSFB-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; NOSFB-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; NOSFB-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; NOSFB-NEXT: addi sp, sp, 32
+; NOSFB-NEXT: ret
+;
+; SFB-LABEL: sextw_removal_ccor:
+; SFB: # %bb.0: # %bb
+; SFB-NEXT: addi sp, sp, -32
+; SFB-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; SFB-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; SFB-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; SFB-NEXT: mv s0, a3
+; SFB-NEXT: andi a0, a0, 1
+; SFB-NEXT: mv s1, a2
+; SFB-NEXT: beqz a0, .LBB15_4
+; SFB-NEXT: # %bb.3: # %bb
+; SFB-NEXT: or s0, a3, a1
+; SFB-NEXT: .LBB15_4: # %bb
+; SFB-NEXT: .LBB15_1: # %bb2
+; SFB-NEXT: # =>This Inner Loop Header: Depth=1
+; SFB-NEXT: mv a0, s0
+; SFB-NEXT: call bar@plt
+; SFB-NEXT: sllw s0, s0, s1
+; SFB-NEXT: bnez a0, .LBB15_1
+; SFB-NEXT: # %bb.2: # %bb7
+; SFB-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; SFB-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; SFB-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; SFB-NEXT: addi sp, sp, 32
+; SFB-NEXT: ret
+bb:
+ %sel = select i1 %c, i32 %arg, i32 0
+ %or = or i32 %sel, %arg2
+ br label %bb2
+
+bb2: ; preds = %bb2, %bb
+ %i3 = phi i32 [ %or, %bb ], [ %i5, %bb2 ]
+ %i4 = tail call signext i32 @bar(i32 signext %i3)
+ %i5 = shl i32 %i3, %arg1
+ %i6 = icmp eq i32 %i4, 0
+ br i1 %i6, label %bb7, label %bb2
+
+bb7: ; preds = %bb2
+ ret void
+}
+declare signext i32 @bar(i32 signext)
+
+define void @sextw_removal_ccaddw(i1 %c, i32 signext %arg, i32 signext %arg1, i32 %arg2) nounwind {
+; NOSFB-LABEL: sextw_removal_ccaddw:
+; NOSFB: # %bb.0: # %bb
+; NOSFB-NEXT: addi sp, sp, -32
+; NOSFB-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; NOSFB-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; NOSFB-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; NOSFB-NEXT: mv s0, a2
+; NOSFB-NEXT: slli a0, a0, 63
+; NOSFB-NEXT: srai a0, a0, 63
+; NOSFB-NEXT: and a0, a0, a3
+; NOSFB-NEXT: addw s1, a0, a1
+; NOSFB-NEXT: .LBB16_1: # %bb2
+; NOSFB-NEXT: # =>This Inner Loop Header: Depth=1
+; NOSFB-NEXT: mv a0, s1
+; NOSFB-NEXT: call bar@plt
+; NOSFB-NEXT: sllw s1, s1, s0
+; NOSFB-NEXT: bnez a0, .LBB16_1
+; NOSFB-NEXT: # %bb.2: # %bb7
+; NOSFB-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; NOSFB-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; NOSFB-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; NOSFB-NEXT: addi sp, sp, 32
+; NOSFB-NEXT: ret
+;
+; SFB-LABEL: sextw_removal_ccaddw:
+; SFB: # %bb.0: # %bb
+; SFB-NEXT: addi sp, sp, -32
+; SFB-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; SFB-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; SFB-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; SFB-NEXT: mv s0, a1
+; SFB-NEXT: andi a0, a0, 1
+; SFB-NEXT: mv s1, a2
+; SFB-NEXT: beqz a0, .LBB16_4
+; SFB-NEXT: # %bb.3: # %bb
+; SFB-NEXT: addw s0, a1, a3
+; SFB-NEXT: .LBB16_4: # %bb
+; SFB-NEXT: .LBB16_1: # %bb2
+; SFB-NEXT: # =>This Inner Loop Header: Depth=1
+; SFB-NEXT: mv a0, s0
+; SFB-NEXT: call bar@plt
+; SFB-NEXT: sllw s0, s0, s1
+; SFB-NEXT: bnez a0, .LBB16_1
+; SFB-NEXT: # %bb.2: # %bb7
+; SFB-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; SFB-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; SFB-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; SFB-NEXT: addi sp, sp, 32
+; SFB-NEXT: ret
+bb:
+ %sel = select i1 %c, i32 %arg2, i32 0
+ %or = add i32 %sel, %arg
+ br label %bb2
+
+bb2: ; preds = %bb2, %bb
+ %i3 = phi i32 [ %or, %bb ], [ %i5, %bb2 ]
+ %i4 = tail call signext i32 @bar(i32 signext %i3)
+ %i5 = shl i32 %i3, %arg1
+ %i6 = icmp eq i32 %i4, 0
+ br i1 %i6, label %bb7, label %bb2
+
+bb7: ; preds = %bb2
+ ret void
+}
generated by cgit v1.1 at 2025-08-03 22:02:26 +0000