diff options
| -rw-r--r-- | llvm/lib/Support/RISCVISAInfo.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVFeatures.td | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/attributes.ll | 8 |
3 files changed, 12 insertions, 6 deletions
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 482811e..da1bd12 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -925,6 +925,8 @@ static const char *ImpliedExtsZfhmin[] = {"f"}; static const char *ImpliedExtsZfinx[] = {"zicsr"}; static const char *ImpliedExtsZhinx[] = {"zfinx"}; static const char *ImpliedExtsZhinxmin[] = {"zfinx"}; +static const char *ImpliedExtsZicntr[] = {"zicsr"}; +static const char *ImpliedExtsZihpm[] = {"zicsr"}; static const char *ImpliedExtsZk[] = {"zkn", "zkt", "zkr"}; static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"}; @@ -980,6 +982,8 @@ static constexpr ImpliedExtsEntry ImpliedExts[] = { {{"zfinx"}, {ImpliedExtsZfinx}}, {{"zhinx"}, {ImpliedExtsZhinx}}, {{"zhinxmin"}, {ImpliedExtsZhinxmin}}, + {{"zicntr"}, {ImpliedExtsZicntr}}, + {{"zihpm"}, {ImpliedExtsZihpm}}, {{"zk"}, {ImpliedExtsZk}}, {{"zkn"}, {ImpliedExtsZkn}}, {{"zks"}, {ImpliedExtsZks}}, diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 5bf634e..47605ee 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -88,11 +88,13 @@ def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">, def FeatureStdExtZicntr : SubtargetFeature<"zicntr", "HasStdExtZicntr", "true", - "'zicntr' (Base Counters and Timers)">; + "'zicntr' (Base Counters and Timers)", + [FeatureStdExtZicsr]>; def FeatureStdExtZihpm : SubtargetFeature<"zihpm", "HasStdExtZihpm", "true", - "'zihpm' (Hardware Performance Counters)">; + "'zihpm' (Hardware Performance Counters)", + [FeatureStdExtZicsr]>; def FeatureStdExtZfhmin : SubtargetFeature<"zfhmin", "HasStdExtZfhmin", "true", diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 19a19c8..6c2f3ac 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -205,8 +205,8 @@ ; RV32ZCF: .attribute 5, "rv32i2p1_zcf1p0" ; RV32ZICSR: .attribute 5, "rv32i2p1_zicsr2p0" ; RV32ZIFENCEI: .attribute 5, "rv32i2p1_zifencei2p0" -; RV32ZICNTR: .attribute 5, "rv32i2p1_zicntr1p0" -; RV32ZIHPM: .attribute 5, "rv32i2p1_zihpm1p0" +; RV32ZICNTR: .attribute 5, "rv32i2p1_zicntr1p0_zicsr2p0" +; RV32ZIHPM: .attribute 5, "rv32i2p1_zicsr2p0_zihpm1p0" ; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p2" ; RV32ZVBB: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p5_zve32x1p0_zvl32b1p0" ; RV32ZVBC: .attribute 5, "rv32i2p1_zicsr2p0_zvbc0p5_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0" @@ -282,8 +282,8 @@ ; RV64ZCD: .attribute 5, "rv64i2p1_zcd1p0" ; RV64ZICSR: .attribute 5, "rv64i2p1_zicsr2p0" ; RV64ZIFENCEI: .attribute 5, "rv64i2p1_zifencei2p0" -; RV64ZICNTR: .attribute 5, "rv64i2p1_zicntr1p0" -; RV64ZIHPM: .attribute 5, "rv64i2p1_zihpm1p0" +; RV64ZICNTR: .attribute 5, "rv64i2p1_zicntr1p0_zicsr2p0" +; RV64ZIHPM: .attribute 5, "rv64i2p1_zicsr2p0_zihpm1p0" ; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa0p2" ; RV64ZVBB: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p5_zve32x1p0_zvl32b1p0" ; RV64ZVBC: .attribute 5, "rv64i2p1_zicsr2p0_zvbc0p5_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0" |