diff options
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll | 249 |
1 files changed, 243 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll index fb1e46d..ea9334a 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll @@ -1,13 +1,100 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck --check-prefixes=GCN,GFX942 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx942 -global-isel < %s | FileCheck --check-prefixes=GCN,GISEL %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx942 -stress-regalloc=10 < %s | FileCheck --check-prefixes=GCN,GFX942 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx942 -stress-regalloc=10 -global-isel < %s | FileCheck --check-prefixes=GCN,GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck --check-prefixes=GFX942,GFX942-SDAG %s +; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck --check-prefixes=GFX942,GFX942-GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx942 -stress-regalloc=10 < %s | FileCheck --check-prefixes=GFX942-STRESS,GFX942-SDAG-STRESS %s +; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx942 -stress-regalloc=10 < %s | FileCheck --check-prefixes=GFX942-STRESS,GFX942-GISEL-STRESS %s declare <4 x float> @llvm.amdgcn.mfma.f32.16x16x8.xf32(<2 x float>, <2 x float>, <4 x float>, i32, i32, i32) declare <16 x float> @llvm.amdgcn.mfma.f32.32x32x4.xf32(<2 x float>, <2 x float>, <16 x float>, i32, i32, i32) define amdgpu_kernel void @test_mfma_f32_16x16x8xf32(ptr addrspace(1) %arg) #0 { +; GFX942-SDAG-LABEL: test_mfma_f32_16x16x8xf32: +; GFX942-SDAG: ; %bb.0: ; %bb +; GFX942-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, 1.0 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, 2.0 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0x40400000 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, 4.0 +; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-SDAG-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, 0 +; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a0, s0 +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a1, s1 +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a2, s2 +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a3, s3 +; GFX942-SDAG-NEXT: s_nop 1 +; GFX942-SDAG-NEXT: v_mfma_f32_16x16x8_xf32 a[0:3], v[4:5], v[0:1], a[0:3] cbsz:1 abid:2 blgp:3 +; GFX942-SDAG-NEXT: s_nop 6 +; GFX942-SDAG-NEXT: global_store_dwordx4 v2, a[0:3], s[6:7] +; GFX942-SDAG-NEXT: s_endpgm +; +; GFX942-GISEL-LABEL: test_mfma_f32_16x16x8xf32: +; GFX942-GISEL: ; %bb.0: ; %bb +; GFX942-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24 +; GFX942-GISEL-NEXT: s_mov_b32 s4, 1.0 +; GFX942-GISEL-NEXT: s_mov_b32 s5, 2.0 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[4:5] +; GFX942-GISEL-NEXT: s_mov_b32 s4, 0x40400000 +; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-GISEL-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0 +; GFX942-GISEL-NEXT: s_mov_b32 s5, 4.0 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5] +; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a0, s0 +; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a1, s1 +; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a2, s2 +; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a3, s3 +; GFX942-GISEL-NEXT: s_nop 1 +; GFX942-GISEL-NEXT: v_mfma_f32_16x16x8_xf32 a[0:3], v[0:1], v[2:3], a[0:3] cbsz:1 abid:2 blgp:3 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, 0 +; GFX942-GISEL-NEXT: s_nop 5 +; GFX942-GISEL-NEXT: global_store_dwordx4 v0, a[0:3], s[6:7] +; GFX942-GISEL-NEXT: s_endpgm +; +; GFX942-SDAG-STRESS-LABEL: test_mfma_f32_16x16x8xf32: +; GFX942-SDAG-STRESS: ; %bb.0: ; %bb +; GFX942-SDAG-STRESS-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24 +; GFX942-SDAG-STRESS-NEXT: v_mov_b32_e32 v0, 1.0 +; GFX942-SDAG-STRESS-NEXT: v_mov_b32_e32 v1, 2.0 +; GFX942-SDAG-STRESS-NEXT: v_mov_b32_e32 v2, 0x40400000 +; GFX942-SDAG-STRESS-NEXT: v_mov_b32_e32 v3, 4.0 +; GFX942-SDAG-STRESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-SDAG-STRESS-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0 +; GFX942-SDAG-STRESS-NEXT: v_mov_b32_e32 v4, 0 +; GFX942-SDAG-STRESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-SDAG-STRESS-NEXT: v_accvgpr_write_b32 a0, s0 +; GFX942-SDAG-STRESS-NEXT: v_accvgpr_write_b32 a1, s1 +; GFX942-SDAG-STRESS-NEXT: v_accvgpr_write_b32 a2, s2 +; GFX942-SDAG-STRESS-NEXT: v_accvgpr_write_b32 a3, s3 +; GFX942-SDAG-STRESS-NEXT: s_nop 1 +; GFX942-SDAG-STRESS-NEXT: v_mfma_f32_16x16x8_xf32 a[0:3], v[0:1], v[2:3], a[0:3] cbsz:1 abid:2 blgp:3 +; GFX942-SDAG-STRESS-NEXT: s_nop 6 +; GFX942-SDAG-STRESS-NEXT: global_store_dwordx4 v4, a[0:3], s[6:7] +; GFX942-SDAG-STRESS-NEXT: s_endpgm +; +; GFX942-GISEL-STRESS-LABEL: test_mfma_f32_16x16x8xf32: +; GFX942-GISEL-STRESS: ; %bb.0: ; %bb +; GFX942-GISEL-STRESS-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24 +; GFX942-GISEL-STRESS-NEXT: s_mov_b32 s0, 1.0 +; GFX942-GISEL-STRESS-NEXT: s_mov_b32 s2, 0x40400000 +; GFX942-GISEL-STRESS-NEXT: s_mov_b32 s1, 2.0 +; GFX942-GISEL-STRESS-NEXT: s_mov_b32 s3, 4.0 +; GFX942-GISEL-STRESS-NEXT: v_mov_b64_e32 v[0:1], s[0:1] +; GFX942-GISEL-STRESS-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX942-GISEL-STRESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-GISEL-STRESS-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0 +; GFX942-GISEL-STRESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-GISEL-STRESS-NEXT: v_accvgpr_write_b32 a0, s0 +; GFX942-GISEL-STRESS-NEXT: v_accvgpr_write_b32 a1, s1 +; GFX942-GISEL-STRESS-NEXT: v_accvgpr_write_b32 a2, s2 +; GFX942-GISEL-STRESS-NEXT: v_accvgpr_write_b32 a3, s3 +; GFX942-GISEL-STRESS-NEXT: s_nop 1 +; GFX942-GISEL-STRESS-NEXT: v_mfma_f32_16x16x8_xf32 a[0:3], v[0:1], v[2:3], a[0:3] cbsz:1 abid:2 blgp:3 +; GFX942-GISEL-STRESS-NEXT: v_mov_b32_e32 v0, 0 +; GFX942-GISEL-STRESS-NEXT: s_nop 5 +; GFX942-GISEL-STRESS-NEXT: global_store_dwordx4 v0, a[0:3], s[6:7] +; GFX942-GISEL-STRESS-NEXT: s_endpgm bb: %in.1 = load <4 x float>, ptr addrspace(1) %arg %mai.1 = tail call <4 x float> @llvm.amdgcn.mfma.f32.16x16x8.xf32(<2 x float> <float 1.0, float 2.0>, <2 x float> <float 3.0, float 4.0>, <4 x float> %in.1, i32 1, i32 2, i32 3) @@ -16,6 +103,157 @@ bb: } define amdgpu_kernel void @test_mfma_f32_32x32x4xf32(ptr addrspace(1) %arg) #0 { +; GFX942-SDAG-LABEL: test_mfma_f32_32x32x4xf32: +; GFX942-SDAG: ; %bb.0: ; %bb +; GFX942-SDAG-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x24 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, 1.0 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, 2.0 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0x40400000 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, 4.0 +; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-SDAG-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0 +; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a0, s0 +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a1, s1 +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a2, s2 +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a3, s3 +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a4, s4 +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a5, s5 +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a6, s6 +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a7, s7 +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a8, s8 +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a9, s9 +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a10, s10 +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a11, s11 +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a12, s12 +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a13, s13 +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a14, s14 +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a15, s15 +; GFX942-SDAG-NEXT: s_nop 1 +; GFX942-SDAG-NEXT: v_mfma_f32_32x32x4_xf32 a[0:15], v[2:3], v[0:1], a[0:15] cbsz:1 abid:2 blgp:3 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v0, 0 +; GFX942-SDAG-NEXT: s_nop 7 +; GFX942-SDAG-NEXT: s_nop 1 +; GFX942-SDAG-NEXT: global_store_dwordx4 v0, a[12:15], s[16:17] offset:48 +; GFX942-SDAG-NEXT: global_store_dwordx4 v0, a[8:11], s[16:17] offset:32 +; GFX942-SDAG-NEXT: global_store_dwordx4 v0, a[4:7], s[16:17] offset:16 +; GFX942-SDAG-NEXT: global_store_dwordx4 v0, a[0:3], s[16:17] +; GFX942-SDAG-NEXT: s_endpgm +; +; GFX942-GISEL-LABEL: test_mfma_f32_32x32x4xf32: +; GFX942-GISEL: ; %bb.0: ; %bb +; GFX942-GISEL-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x24 +; GFX942-GISEL-NEXT: s_mov_b32 s18, 1.0 +; GFX942-GISEL-NEXT: s_mov_b32 s19, 2.0 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[18:19] +; GFX942-GISEL-NEXT: s_mov_b32 s18, 0x40400000 +; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-GISEL-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0 +; GFX942-GISEL-NEXT: s_mov_b32 s19, 4.0 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[18:19] +; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a0, s0 +; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a1, s1 +; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a2, s2 +; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a3, s3 +; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a4, s4 +; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a5, s5 +; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a6, s6 +; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a7, s7 +; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a8, s8 +; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a9, s9 +; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a10, s10 +; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a11, s11 +; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a12, s12 +; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a13, s13 +; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a14, s14 +; GFX942-GISEL-NEXT: v_accvgpr_write_b32 a15, s15 +; GFX942-GISEL-NEXT: s_nop 1 +; GFX942-GISEL-NEXT: v_mfma_f32_32x32x4_xf32 a[0:15], v[0:1], v[2:3], a[0:15] cbsz:1 abid:2 blgp:3 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v0, 0 +; GFX942-GISEL-NEXT: s_nop 7 +; GFX942-GISEL-NEXT: s_nop 1 +; GFX942-GISEL-NEXT: global_store_dwordx4 v0, a[0:3], s[16:17] +; GFX942-GISEL-NEXT: global_store_dwordx4 v0, a[4:7], s[16:17] offset:16 +; GFX942-GISEL-NEXT: global_store_dwordx4 v0, a[8:11], s[16:17] offset:32 +; GFX942-GISEL-NEXT: global_store_dwordx4 v0, a[12:15], s[16:17] offset:48 +; GFX942-GISEL-NEXT: s_endpgm +; +; GFX942-SDAG-STRESS-LABEL: test_mfma_f32_32x32x4xf32: +; GFX942-SDAG-STRESS: ; %bb.0: ; %bb +; GFX942-SDAG-STRESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x24 +; GFX942-SDAG-STRESS-NEXT: v_mov_b32_e32 v0, 1.0 +; GFX942-SDAG-STRESS-NEXT: v_mov_b32_e32 v1, 2.0 +; GFX942-SDAG-STRESS-NEXT: v_mov_b32_e32 v2, 0x40400000 +; GFX942-SDAG-STRESS-NEXT: v_mov_b32_e32 v3, 4.0 +; GFX942-SDAG-STRESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-SDAG-STRESS-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0 +; GFX942-SDAG-STRESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-SDAG-STRESS-NEXT: v_accvgpr_write_b32 a0, s0 +; GFX942-SDAG-STRESS-NEXT: v_accvgpr_write_b32 a1, s1 +; GFX942-SDAG-STRESS-NEXT: v_accvgpr_write_b32 a2, s2 +; GFX942-SDAG-STRESS-NEXT: v_accvgpr_write_b32 a3, s3 +; GFX942-SDAG-STRESS-NEXT: v_accvgpr_write_b32 a4, s4 +; GFX942-SDAG-STRESS-NEXT: v_accvgpr_write_b32 a5, s5 +; GFX942-SDAG-STRESS-NEXT: v_accvgpr_write_b32 a6, s6 +; GFX942-SDAG-STRESS-NEXT: v_accvgpr_write_b32 a7, s7 +; GFX942-SDAG-STRESS-NEXT: v_accvgpr_write_b32 a8, s8 +; GFX942-SDAG-STRESS-NEXT: v_accvgpr_write_b32 a9, s9 +; GFX942-SDAG-STRESS-NEXT: v_accvgpr_write_b32 a10, s10 +; GFX942-SDAG-STRESS-NEXT: v_accvgpr_write_b32 a11, s11 +; GFX942-SDAG-STRESS-NEXT: v_accvgpr_write_b32 a12, s12 +; GFX942-SDAG-STRESS-NEXT: v_accvgpr_write_b32 a13, s13 +; GFX942-SDAG-STRESS-NEXT: v_accvgpr_write_b32 a14, s14 +; GFX942-SDAG-STRESS-NEXT: v_accvgpr_write_b32 a15, s15 +; GFX942-SDAG-STRESS-NEXT: s_nop 1 +; GFX942-SDAG-STRESS-NEXT: v_mfma_f32_32x32x4_xf32 a[0:15], v[0:1], v[2:3], a[0:15] cbsz:1 abid:2 blgp:3 +; GFX942-SDAG-STRESS-NEXT: v_mov_b32_e32 v0, 0 +; GFX942-SDAG-STRESS-NEXT: s_nop 7 +; GFX942-SDAG-STRESS-NEXT: s_nop 1 +; GFX942-SDAG-STRESS-NEXT: global_store_dwordx4 v0, a[12:15], s[16:17] offset:48 +; GFX942-SDAG-STRESS-NEXT: global_store_dwordx4 v0, a[8:11], s[16:17] offset:32 +; GFX942-SDAG-STRESS-NEXT: global_store_dwordx4 v0, a[4:7], s[16:17] offset:16 +; GFX942-SDAG-STRESS-NEXT: global_store_dwordx4 v0, a[0:3], s[16:17] +; GFX942-SDAG-STRESS-NEXT: s_endpgm +; +; GFX942-GISEL-STRESS-LABEL: test_mfma_f32_32x32x4xf32: +; GFX942-GISEL-STRESS: ; %bb.0: ; %bb +; GFX942-GISEL-STRESS-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x24 +; GFX942-GISEL-STRESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-GISEL-STRESS-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0 +; GFX942-GISEL-STRESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-GISEL-STRESS-NEXT: v_accvgpr_write_b32 a0, s0 +; GFX942-GISEL-STRESS-NEXT: v_accvgpr_write_b32 a1, s1 +; GFX942-GISEL-STRESS-NEXT: v_accvgpr_write_b32 a2, s2 +; GFX942-GISEL-STRESS-NEXT: v_accvgpr_write_b32 a3, s3 +; GFX942-GISEL-STRESS-NEXT: v_accvgpr_write_b32 a4, s4 +; GFX942-GISEL-STRESS-NEXT: v_accvgpr_write_b32 a5, s5 +; GFX942-GISEL-STRESS-NEXT: v_accvgpr_write_b32 a6, s6 +; GFX942-GISEL-STRESS-NEXT: v_accvgpr_write_b32 a7, s7 +; GFX942-GISEL-STRESS-NEXT: v_accvgpr_write_b32 a8, s8 +; GFX942-GISEL-STRESS-NEXT: v_accvgpr_write_b32 a9, s9 +; GFX942-GISEL-STRESS-NEXT: v_accvgpr_write_b32 a10, s10 +; GFX942-GISEL-STRESS-NEXT: v_accvgpr_write_b32 a11, s11 +; GFX942-GISEL-STRESS-NEXT: v_accvgpr_write_b32 a12, s12 +; GFX942-GISEL-STRESS-NEXT: v_accvgpr_write_b32 a13, s13 +; GFX942-GISEL-STRESS-NEXT: v_accvgpr_write_b32 a14, s14 +; GFX942-GISEL-STRESS-NEXT: v_accvgpr_write_b32 a15, s15 +; GFX942-GISEL-STRESS-NEXT: s_mov_b32 s0, 1.0 +; GFX942-GISEL-STRESS-NEXT: s_mov_b32 s1, 2.0 +; GFX942-GISEL-STRESS-NEXT: v_mov_b64_e32 v[0:1], s[0:1] +; GFX942-GISEL-STRESS-NEXT: s_mov_b32 s0, 0x40400000 +; GFX942-GISEL-STRESS-NEXT: s_mov_b32 s1, 4.0 +; GFX942-GISEL-STRESS-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX942-GISEL-STRESS-NEXT: s_nop 1 +; GFX942-GISEL-STRESS-NEXT: v_mfma_f32_32x32x4_xf32 a[0:15], v[0:1], v[2:3], a[0:15] cbsz:1 abid:2 blgp:3 +; GFX942-GISEL-STRESS-NEXT: v_mov_b32_e32 v0, 0 +; GFX942-GISEL-STRESS-NEXT: s_nop 7 +; GFX942-GISEL-STRESS-NEXT: s_nop 1 +; GFX942-GISEL-STRESS-NEXT: global_store_dwordx4 v0, a[0:3], s[16:17] +; GFX942-GISEL-STRESS-NEXT: global_store_dwordx4 v0, a[4:7], s[16:17] offset:16 +; GFX942-GISEL-STRESS-NEXT: global_store_dwordx4 v0, a[8:11], s[16:17] offset:32 +; GFX942-GISEL-STRESS-NEXT: global_store_dwordx4 v0, a[12:15], s[16:17] offset:48 +; GFX942-GISEL-STRESS-NEXT: s_endpgm bb: %in.1 = load <16 x float>, ptr addrspace(1) %arg %mai.1 = tail call <16 x float> @llvm.amdgcn.mfma.f32.32x32x4.xf32(<2 x float> <float 1.0, float 2.0>, <2 x float> <float 3.0, float 4.0>, <16 x float> %in.1, i32 1, i32 2, i32 3) @@ -25,6 +263,5 @@ bb: attributes #0 = { "amdgpu-flat-work-group-size"="1,256" } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; GCN: {{.*}} ; GFX942: {{.*}} -; GISEL: {{.*}} +; GFX942-STRESS: {{.*}} |