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| author | Joshua Cao <cao.joshua@yahoo.com> | 2023-05-30 01:53:06 -0700 |
|---|---|---|
| committer | Joshua Cao <cao.joshua@yahoo.com> | 2023-05-31 21:05:17 -0700 |
| commit | 6ed152aff4aab6307ecaab64a544d0524ea5f50e (patch) | |
| tree | fea857545df0c5b6e782ac90372be2695a6104b1 /polly/test | |
| parent | 46c59a55e747ed7c0c68e64b13621a5b5e243c83 (diff) | |
| download | llvm-6ed152aff4aab6307ecaab64a544d0524ea5f50e.zip llvm-6ed152aff4aab6307ecaab64a544d0524ea5f50e.tar.gz llvm-6ed152aff4aab6307ecaab64a544d0524ea5f50e.tar.bz2 | |
[SCEV] Compute AddRec range computations using different type BECount
Before this patch, we can only use the MaxBECount for an AddRec's range
computation if the MaxBECount has <= bit width of the AddRec. This patch
reasons that if a MaxBECount has > bit width, and is <= the max value of
AddRec's bit width, we can still use the MaxBECount.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D151698
Diffstat (limited to 'polly/test')
| -rw-r--r-- | polly/test/CodeGen/switch-in-non-affine-region.ll | 14 | ||||
| -rw-r--r-- | polly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_3.ll | 6 |
2 files changed, 10 insertions, 10 deletions
diff --git a/polly/test/CodeGen/switch-in-non-affine-region.ll b/polly/test/CodeGen/switch-in-non-affine-region.ll index 8eeabd98..930755e 100644 --- a/polly/test/CodeGen/switch-in-non-affine-region.ll +++ b/polly/test/CodeGen/switch-in-non-affine-region.ll @@ -14,13 +14,13 @@ ; } ; } ; -; CHECK: polly.stmt.if.then: -; CHECK: %[[trunc:.*]] = trunc i64 %polly.indvar to i32 -; CHECK: %p_rem = srem i32 %[[trunc]], 4 -; CHECK: switch i32 %p_rem, label %polly.stmt.sw.epilog [ -; CHECK: i32 0, label %polly.stmt.sw.bb -; CHECK: i32 1, label %polly.stmt.sw.bb.3 -; CHECK: ] +; CHECK: polly.stmt.if.then: +; CHECK-NEXT: %2 = trunc i64 %polly.indvar to i2 +; CHECK-NEXT: %3 = zext i2 %2 to i32 +; CHECK-NEXT: switch i32 %3, label %polly.stmt.sw.epilog [ +; CHECK-NEXT: i32 0, label %polly.stmt.sw.bb +; CHECK-NEXT: i32 1, label %polly.stmt.sw.bb.3 +; CHECK-NEXT: ] ; target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" diff --git a/polly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_3.ll b/polly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_3.ll index b11675b..463db23 100644 --- a/polly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_3.ll +++ b/polly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_3.ll @@ -14,7 +14,7 @@ ; INNERMOST-NEXT: Invariant Accesses: { ; INNERMOST-NEXT: } ; INNERMOST-NEXT: Context: -; INNERMOST-NEXT: [p_0, p_1, p_2] -> { : 0 <= p_0 <= 2147483647 and 0 <= p_1 <= 1024 and 0 <= p_2 <= 1024 } +; INNERMOST-NEXT: [p_0, p_1, p_2] -> { : 0 <= p_0 <= 1048576 and 0 <= p_1 <= 1024 and 0 <= p_2 <= 1024 } ; INNERMOST-NEXT: Assumed Context: ; INNERMOST-NEXT: [p_0, p_1, p_2] -> { : } ; INNERMOST-NEXT: Invalid Context: @@ -89,9 +89,9 @@ ; ALL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0] ; ALL-NEXT: { Stmt_bb15__TO__bb25[i0, i1] -> MemRef_A[i1] }; ; ALL-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0] -; ALL-NEXT: { Stmt_bb15__TO__bb25[i0, i1] -> MemRef_A[o0] : 0 <= o0 <= 2147483647 }; +; ALL-NEXT: { Stmt_bb15__TO__bb25[i0, i1] -> MemRef_A[o0] : 0 <= o0 <= 1048576 }; ; ALL-NEXT: MayWriteAccess := [Reduction Type: NONE] [Scalar: 0] -; ALL-NEXT: { Stmt_bb15__TO__bb25[i0, i1] -> MemRef_A[o0] : 0 <= o0 <= 2147483647 }; +; ALL-NEXT: { Stmt_bb15__TO__bb25[i0, i1] -> MemRef_A[o0] : 0 <= o0 <= 1048576 }; ; ALL-NEXT: } ; ; void f(int *A) { |