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| author | Craig Topper <craig.topper@sifive.com> | 2025-07-24 21:54:51 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-24 21:54:51 -0700 |
| commit | bd91e8a5bd115be1350d4ad3a7100303511b1d15 (patch) | |
| tree | f4e155b5f30c47be663cb4fd2152d17e4ea1ab23 /llvm/utils | |
| parent | 4b1ca9c072cc36af77afecbc95be3c3c3e764404 (diff) | |
| download | llvm-bd91e8a5bd115be1350d4ad3a7100303511b1d15.zip llvm-bd91e8a5bd115be1350d4ad3a7100303511b1d15.tar.gz llvm-bd91e8a5bd115be1350d4ad3a7100303511b1d15.tar.bz2 | |
[TableGen] Strengthen check for what operands can be an immediate in CompressInstEmitter. (#150568)
Registers can be represented by RegisterOperand, not just RegisterClass.
Instead of trying to block certain classes, only allow Operand.
Diffstat (limited to 'llvm/utils')
| -rw-r--r-- | llvm/utils/TableGen/CompressInstEmitter.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp index 72e45ed..e80adce 100644 --- a/llvm/utils/TableGen/CompressInstEmitter.cpp +++ b/llvm/utils/TableGen/CompressInstEmitter.cpp @@ -275,7 +275,7 @@ void CompressInstEmitter::addDagOperandMapping(const Record *Rec, OperandMap[OpNo].Kind = OpData::Operand; } else if (const auto *II = dyn_cast<IntInit>(Dag->getArg(DAGOpNo))) { // Validate that corresponding instruction operand expects an immediate. - if (OpndRec->isSubClassOf("RegisterClass")) + if (!OpndRec->isSubClassOf("Operand")) PrintFatalError(Rec->getLoc(), "Error in Dag '" + Dag->getAsString() + "' Found immediate: '" + II->getAsString() + |