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| author | XinWang10 <108658776+XinWang10@users.noreply.github.com> | 2024-01-25 22:24:43 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-01-26 14:24:43 +0800 |
| commit | 6d0080b5de26d8a8682ec6169851af3d04e30ccb (patch) | |
| tree | 133ddb654ac15e138e215f4ac6ca1036b3006687 /llvm/utils | |
| parent | df5e431e8dcb555320be7f7ae4d499a11e0b17db (diff) | |
| download | llvm-6d0080b5de26d8a8682ec6169851af3d04e30ccb.zip llvm-6d0080b5de26d8a8682ec6169851af3d04e30ccb.tar.gz llvm-6d0080b5de26d8a8682ec6169851af3d04e30ccb.tar.bz2 | |
[X86] Support promoted ENQCMD, KEYLOCKER and USERMSR (#77293)
R16-R31 was added into GPRs in
https://github.com/llvm/llvm-project/pull/70958,
This patch supports the promoted ENQCMD, KEYLOCKER and USER-MSR
instructions in EVEX space.
RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
Diffstat (limited to 'llvm/utils')
| -rw-r--r-- | llvm/utils/TableGen/X86DisassemblerTables.cpp | 8 | ||||
| -rw-r--r-- | llvm/utils/TableGen/X86RecognizableInstr.cpp | 10 |
2 files changed, 11 insertions, 7 deletions
diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp index 9ee1472..23886a3 100644 --- a/llvm/utils/TableGen/X86DisassemblerTables.cpp +++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp @@ -214,6 +214,8 @@ static inline bool inheritsFrom(InstructionContext child, (VEX_LIG && inheritsFrom(child, IC_EVEX_L_OPSIZE)) || (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE)); case IC_EVEX_OPSIZE_ADSIZE: + case IC_EVEX_XS_ADSIZE: + case IC_EVEX_XD_ADSIZE: return false; case IC_EVEX_K: return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_K)) || @@ -894,8 +896,12 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const { for (unsigned index = 0; index < ATTR_max; ++index) { o.indent(i * 2); - if ((index & ATTR_EVEX) && (index & ATTR_OPSIZE) && (index & ATTR_ADSIZE)) + if ((index & ATTR_EVEX) && (index & ATTR_ADSIZE) && (index & ATTR_OPSIZE)) o << "IC_EVEX_OPSIZE_ADSIZE"; + else if ((index & ATTR_EVEX) && (index & ATTR_ADSIZE) && (index & ATTR_XD)) + o << "IC_EVEX_XD_ADSIZE"; + else if ((index & ATTR_EVEX) && (index & ATTR_ADSIZE) && (index & ATTR_XS)) + o << "IC_EVEX_XS_ADSIZE"; else if (index & ATTR_EVEXNF) { o << "IC_EVEX"; if (index & ATTR_REXW) diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp index fb43067..18f9610 100644 --- a/llvm/utils/TableGen/X86RecognizableInstr.cpp +++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp @@ -188,6 +188,7 @@ void RecognizableInstr::processInstr(DisassemblerTables &tables, #define EVEX_NF(n) (HasEVEX_NF ? n##_NF : n) #define EVEX_B_NF(n) (HasEVEX_B ? EVEX_NF(n##_B) : EVEX_NF(n)) +#define EVEX_KB_ADSIZE(n) AdSize == X86Local::AdSize32 ? n##_ADSIZE : EVEX_KB(n) InstructionContext RecognizableInstr::insnContext() const { InstructionContext insnContext; @@ -277,14 +278,11 @@ InstructionContext RecognizableInstr::insnContext() const { } // No L, no W else if (OpPrefix == X86Local::PD) { - if (AdSize == X86Local::AdSize32) - insnContext = IC_EVEX_OPSIZE_ADSIZE; - else - insnContext = EVEX_KB(IC_EVEX_OPSIZE); + insnContext = EVEX_KB_ADSIZE(IC_EVEX_OPSIZE); } else if (OpPrefix == X86Local::XD) - insnContext = EVEX_KB(IC_EVEX_XD); + insnContext = EVEX_KB_ADSIZE(IC_EVEX_XD); else if (OpPrefix == X86Local::XS) - insnContext = EVEX_KB(IC_EVEX_XS); + insnContext = EVEX_KB_ADSIZE(IC_EVEX_XS); else if (OpPrefix == X86Local::PS) insnContext = EVEX_KB(IC_EVEX); else { |