Revert "[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions" (#101612)

Reverts llvm/llvm-project#101452

There are several buildbot failed. Revert first.

4 files changed, 2 insertions, 62 deletions

diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp
index b0acd4ea..7d28c48 100644
--- a/llvm/utils/TableGen/X86DisassemblerTables.cpp
+++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp
@@ -575,31 +575,6 @@ static inline bool inheritsFrom(InstructionContext child,
   case IC_EVEX_W_NF:
   case IC_EVEX_W_B_NF:
     return false;
-  case IC_EVEX_B_U:
-  case IC_EVEX_XS_B_U:
-  case IC_EVEX_XD_B_U:
-  case IC_EVEX_OPSIZE_B_U:
-  case IC_EVEX_W_B_U:
-  case IC_EVEX_W_XS_B_U:
-  case IC_EVEX_W_XD_B_U:
-  case IC_EVEX_W_OPSIZE_B_U:
-  case IC_EVEX_K_B_U:
-  case IC_EVEX_XS_K_B_U:
-  case IC_EVEX_XD_K_B_U:
-  case IC_EVEX_OPSIZE_K_B_U:
-  case IC_EVEX_W_K_B_U:
-  case IC_EVEX_W_XS_K_B_U:
-  case IC_EVEX_W_XD_K_B_U:
-  case IC_EVEX_W_OPSIZE_K_B_U:
-  case IC_EVEX_KZ_B_U:
-  case IC_EVEX_XS_KZ_B_U:
-  case IC_EVEX_XD_KZ_B_U:
-  case IC_EVEX_OPSIZE_KZ_B_U:
-  case IC_EVEX_W_KZ_B_U:
-  case IC_EVEX_W_XS_KZ_B_U:
-  case IC_EVEX_W_XD_KZ_B_U:
-  case IC_EVEX_W_OPSIZE_KZ_B_U:
-    return false;
   default:
     errs() << "Unknown instruction class: "
            << stringForContext((InstructionContext)parent) << "\n";
@@ -951,9 +926,7 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
       else
         o << "IC_VEX";
 
-      if ((index & ATTR_EVEXB) && (index & ATTR_EVEXU))
-        ; // Ignore ATTR_VEXL and ATTR_EVEXL2 under YMM rounding.
-      else if ((index & ATTR_EVEX) && (index & ATTR_EVEXL2))
+      if ((index & ATTR_EVEX) && (index & ATTR_EVEXL2))
         o << "_L2";
       else if (index & ATTR_VEXL)
         o << "_L";
@@ -976,9 +949,6 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
 
         if (index & ATTR_EVEXB)
           o << "_B";
-
-        if ((index & ATTR_EVEXB) && (index & ATTR_EVEXU))
-          o << "_U";
       }
     } else if ((index & ATTR_64BIT) && (index & ATTR_REX2))
       o << "IC_64BIT_REX2";
diff --git a/llvm/utils/TableGen/X86ManualInstrMapping.def b/llvm/utils/TableGen/X86ManualInstrMapping.def
index f0154b80..58f5449 100644
--- a/llvm/utils/TableGen/X86ManualInstrMapping.def
+++ b/llvm/utils/TableGen/X86ManualInstrMapping.def
@@ -77,10 +77,6 @@ ENTRY(VMOVDQU16Z256rr, VMOVDQUYrr)
 ENTRY(VMOVDQU8Z256mr, VMOVDQUYmr)
 ENTRY(VMOVDQU8Z256rm, VMOVDQUYrm)
 ENTRY(VMOVDQU8Z256rr, VMOVDQUYrr)
-ENTRY(VMPSADBWZ128rmi, VMPSADBWrmi)
-ENTRY(VMPSADBWZ128rri, VMPSADBWrri)
-ENTRY(VMPSADBWZ256rmi, VMPSADBWYrmi)
-ENTRY(VMPSADBWZ256rri, VMPSADBWYrri)
 ENTRY(VSHUFF32X4Z256rmi, VPERM2F128rm)
 ENTRY(VSHUFF32X4Z256rri, VPERM2F128rr)
 ENTRY(VSHUFF64X2Z256rmi, VPERM2F128rm)
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index 6aae57e..a2bc037 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -126,7 +126,6 @@ RecognizableInstrBase::RecognizableInstrBase(const CodeGenInstruction &insn) {
   HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
   HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
   HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
-  HasEVEX_U = Rec->getValueAsBit("hasEVEX_U");
   HasEVEX_NF = Rec->getValueAsBit("hasEVEX_NF");
   HasTwoConditionalOps = Rec->getValueAsBit("hasTwoConditionalOps");
   IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
@@ -192,8 +191,6 @@ void RecognizableInstr::processInstr(DisassemblerTables &tables,
 #define EVEX_NF(n) (HasEVEX_NF ? n##_NF : n)
 #define EVEX_B_NF(n) (HasEVEX_B ? EVEX_NF(n##_B) : EVEX_NF(n))
 #define EVEX_KB_ADSIZE(n) AdSize == X86Local::AdSize32 ? n##_ADSIZE : EVEX_KB(n)
-#define EVEX_KB_U(n)                                                           \
-  (HasEVEX_KZ ? n##_KZ_B_U : (HasEVEX_K ? n##_K_B_U : n##_B_U))
 
 InstructionContext RecognizableInstr::insnContext() const {
   InstructionContext insnContext;
@@ -203,28 +200,7 @@ InstructionContext RecognizableInstr::insnContext() const {
       errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
       llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
     }
-    if (EncodeRC && HasEVEX_U) {
-      // EVEX_U
-      if (HasREX_W) {
-        if (OpPrefix == X86Local::PD)
-          insnContext = EVEX_KB_U(IC_EVEX_W_OPSIZE);
-        else if (OpPrefix == X86Local::XS)
-          insnContext = EVEX_KB_U(IC_EVEX_W_XS);
-        else if (OpPrefix == X86Local::XD)
-          insnContext = EVEX_KB_U(IC_EVEX_W_XD);
-        else if (OpPrefix == X86Local::PS)
-          insnContext = EVEX_KB_U(IC_EVEX_W);
-      } else {
-        if (OpPrefix == X86Local::PD)
-          insnContext = EVEX_KB_U(IC_EVEX_OPSIZE);
-        else if (OpPrefix == X86Local::XS)
-          insnContext = EVEX_KB_U(IC_EVEX_XS);
-        else if (OpPrefix == X86Local::XD)
-          insnContext = EVEX_KB_U(IC_EVEX_XD);
-        else if (OpPrefix == X86Local::PS)
-          insnContext = EVEX_KB_U(IC_EVEX);
-      }
-    } else if (HasEVEX_NF) {
+    if (HasEVEX_NF) {
       if (OpPrefix == X86Local::PD)
         insnContext = EVEX_B_NF(IC_EVEX_OPSIZE);
       else if (HasREX_W)
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.h b/llvm/utils/TableGen/X86RecognizableInstr.h
index eb2cee7..12fb417 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.h
+++ b/llvm/utils/TableGen/X86RecognizableInstr.h
@@ -214,8 +214,6 @@ struct RecognizableInstrBase {
   bool HasEVEX_KZ;
   /// The hasEVEX_B field from the record
   bool HasEVEX_B;
-  /// The hasEVEX_U field from the record
-  bool HasEVEX_U;
   /// The hasEVEX_NF field from the record
   bool HasEVEX_NF;
   /// The hasTwoConditionalOps field from the record