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| author | Sudharsan Veeravalli <quic_svs@quicinc.com> | 2025-07-15 04:52:51 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-15 04:52:51 +0530 |
| commit | 085e8f1e520b91f5ed40e5b09f458bb2c4d7c0e0 (patch) | |
| tree | c5b79ed751bd966ee4901eef71df6da7fa741268 /llvm/utils | |
| parent | ad9a9537e6222853da3966abd978548f0b62eab8 (diff) | |
| download | llvm-085e8f1e520b91f5ed40e5b09f458bb2c4d7c0e0.zip llvm-085e8f1e520b91f5ed40e5b09f458bb2c4d7c0e0.tar.gz llvm-085e8f1e520b91f5ed40e5b09f458bb2c4d7c0e0.tar.bz2 | |
[RISCV] Relax destination instruction dag operand matching in CompresInstEmitter (#148660)
We have some 48-bit instructions in the `Xqci` spec that currently
cannot be compressed to their 32-bit variants due to the constraint in
`CompressInstEmitter` on destination instruction operands not being
allowed to mismatch with the DAG operands.
For eg. the` QC_E_ADDI` instruction can be compressed to the `ADDI`
instruction when the immediate is signed-12 bit but this is currently
not possible since the `QC_E_ADDI` instruction has `GPRNoX0` register
operands while the `ADDI` instruction has `GPR` register operands
leading to an operand type validation error.
I think we can remove the check that only source instruction operands
can mismatch with the corresponding DAG operands and rely on the fact
that we check if the DAG register operand type is a subclass of the
instruction register operand type.
Diffstat (limited to 'llvm/utils')
| -rw-r--r-- | llvm/utils/TableGen/CompressInstEmitter.cpp | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp index d8626a0..afc892b 100644 --- a/llvm/utils/TableGen/CompressInstEmitter.cpp +++ b/llvm/utils/TableGen/CompressInstEmitter.cpp @@ -171,10 +171,6 @@ bool CompressInstEmitter::validateTypes(const Record *DagOpType, bool IsSourceInst) { if (DagOpType == InstOpType) return true; - // Only source instruction operands are allowed to not match Input Dag - // operands. - if (!IsSourceInst) - return false; if (DagOpType->isSubClassOf("RegisterClass") && InstOpType->isSubClassOf("RegisterClass")) { @@ -258,9 +254,9 @@ void CompressInstEmitter::addDagOperandMapping(const Record *Rec, continue; } // Validate that Dag operand type matches the type defined in the - // corresponding instruction. Operands in the input Dag pattern are - // allowed to be a subclass of the type specified in corresponding - // instruction operand instead of being an exact match. + // corresponding instruction. Operands in the input and output Dag + // patterns are allowed to be a subclass of the type specified in the + // corresponding instruction operand instead of being an exact match. if (!validateTypes(DI->getDef(), OpndRec, IsSourceInst)) PrintFatalError(Rec->getLoc(), "Error in Dag '" + Dag->getAsString() + |