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authorShengchen Kan <shengchen.kan@intel.com>2023-12-28 21:22:03 +0800
committerGitHub <noreply@github.com>2023-12-28 21:22:03 +0800
commitd79ccee8dc4aea52c146b10603f2a38646ad22fe (patch)
tree58004bb5bf8aacc3d9ca3d26641bfa564d4d62fe /llvm/utils/TableGen/X86DisassemblerTables.cpp
parent50965010821f70536136c121384b9cf5b47ced88 (diff)
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[X86][MC] Support encoding/decoding for APX variant ADD/SUB/ADC/SBB/OR/XOR/NEG/NOT instructions (#76319)
Four variants: promoted legacy, ND (new data destination), NF (no flags update) and NF_ND (NF + ND). The syntax of NF instructions is aligned with GNU binutils. https://sourceware.org/pipermail/binutils/2023-September/129545.html
Diffstat (limited to 'llvm/utils/TableGen/X86DisassemblerTables.cpp')
-rw-r--r--llvm/utils/TableGen/X86DisassemblerTables.cpp21
1 files changed, 20 insertions, 1 deletions
diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp
index 06e7ec3..9ee1472 100644
--- a/llvm/utils/TableGen/X86DisassemblerTables.cpp
+++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp
@@ -563,6 +563,13 @@ static inline bool inheritsFrom(InstructionContext child,
case IC_EVEX_L2_W_XD_KZ_B:
case IC_EVEX_L2_W_OPSIZE_KZ_B:
return false;
+ case IC_EVEX_NF:
+ case IC_EVEX_B_NF:
+ case IC_EVEX_OPSIZE_NF:
+ case IC_EVEX_OPSIZE_B_NF:
+ case IC_EVEX_W_NF:
+ case IC_EVEX_W_B_NF:
+ return false;
default:
errs() << "Unknown instruction class: "
<< stringForContext((InstructionContext)parent) << "\n";
@@ -889,7 +896,19 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
if ((index & ATTR_EVEX) && (index & ATTR_OPSIZE) && (index & ATTR_ADSIZE))
o << "IC_EVEX_OPSIZE_ADSIZE";
- else if ((index & ATTR_EVEX) || (index & ATTR_VEX) || (index & ATTR_VEXL)) {
+ else if (index & ATTR_EVEXNF) {
+ o << "IC_EVEX";
+ if (index & ATTR_REXW)
+ o << "_W";
+ else if (index & ATTR_OPSIZE)
+ o << "_OPSIZE";
+
+ if (index & ATTR_EVEXB)
+ o << "_B";
+
+ o << "_NF";
+ } else if ((index & ATTR_EVEX) || (index & ATTR_VEX) ||
+ (index & ATTR_VEXL)) {
if (index & ATTR_EVEX)
o << "IC_EVEX";
else