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author | Xiang1 Zhang <xiang1.zhang@intel.com> | 2020-07-02 08:36:45 +0800 |
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committer | Xiang1 Zhang <xiang1.zhang@intel.com> | 2020-07-02 08:57:04 +0800 |
commit | aded4f0cc070fcef6763c9a3c2ba764d652b692e (patch) | |
tree | 12be06afe5e1998a21e9be647a144d256341ee35 /llvm/utils/TableGen/X86DisassemblerTables.cpp | |
parent | 99c4207d428bc1e24fed677c67230e27dd3d508f (diff) | |
download | llvm-aded4f0cc070fcef6763c9a3c2ba764d652b692e.zip llvm-aded4f0cc070fcef6763c9a3c2ba764d652b692e.tar.gz llvm-aded4f0cc070fcef6763c9a3c2ba764d652b692e.tar.bz2 |
[X86-64] Support Intel AMX instructions
Summary:
INTEL ADVANCED MATRIX EXTENSIONS (AMX).
AMX is a new programming paradigm, it has a set of 2-dimensional registers
(TILES) representing sub-arrays from a larger 2-dimensional memory image and
operate on TILES.
Spec can be found in Chapter 3 here https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
Reviewers: LuoYuanke, annita.zhang, pengfei, RKSimon, xiangzhangllvm
Reviewed By: xiangzhangllvm
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D82705
Diffstat (limited to 'llvm/utils/TableGen/X86DisassemblerTables.cpp')
-rw-r--r-- | llvm/utils/TableGen/X86DisassemblerTables.cpp | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp index 76e4fd9..3a95df2 100644 --- a/llvm/utils/TableGen/X86DisassemblerTables.cpp +++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp @@ -595,6 +595,7 @@ static ModRMDecisionType getDecisionType(ModRMDecision &decision) { bool satisfiesOneEntry = true; bool satisfiesSplitRM = true; bool satisfiesSplitReg = true; + bool satisfiesSplitRegM = true; bool satisfiesSplitMisc = true; for (unsigned index = 0; index < 256; ++index) { @@ -616,6 +617,10 @@ static ModRMDecisionType getDecisionType(ModRMDecision &decision) { if (((index & 0xc0) != 0xc0) && (decision.instructionIDs[index] != decision.instructionIDs[index&0x38])) satisfiesSplitMisc = false; + + if (((index & 0xc0) == 0xc0) && + (decision.instructionIDs[index] != decision.instructionIDs[index&0xc7])) + satisfiesSplitRegM = false; } if (satisfiesOneEntry) @@ -627,6 +632,9 @@ static ModRMDecisionType getDecisionType(ModRMDecision &decision) { if (satisfiesSplitReg && satisfiesSplitMisc) return MODRM_SPLITREG; + if (satisfiesSplitRegM) + return MODRM_SPLITREGM; + if (satisfiesSplitMisc) return MODRM_SPLITMISC; @@ -691,6 +699,10 @@ void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2, for (unsigned index = 0xc0; index < 256; index += 8) ModRMDecision.push_back(decision.instructionIDs[index]); break; + case MODRM_SPLITREGM: + for (unsigned index = 0xc0; index < 256; index += 8) + ModRMDecision.push_back(decision.instructionIDs[index]); + break; case MODRM_SPLITMISC: for (unsigned index = 0; index < 64; index += 8) ModRMDecision.push_back(decision.instructionIDs[index]); @@ -732,6 +744,9 @@ void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2, case MODRM_SPLITREG: sEntryNumber += 16; break; + case MODRM_SPLITREGM: + sEntryNumber += 8; + break; case MODRM_SPLITMISC: sEntryNumber += 8 + 64; break; |