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author | Nuko Y. <or@dmc.chat> | 2025-05-12 22:10:28 +0000 |
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committer | GitHub <noreply@github.com> | 2025-05-12 15:10:28 -0700 |
commit | 26f97ee9aa413db240c397f96ddd5b0553a57d30 (patch) | |
tree | ae7c176eb0141e41c05e17d5eb7f4c998fc7da16 /llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp | |
parent | 64082912a500d004c53ad1b3425098b495572663 (diff) | |
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[AArch64] Stop reserved registers from being saved in prolog/epilog (#138448)
[GCC's
documentation](https://gcc.gnu.org/onlinedocs/gcc-15.1.0/gcc/Code-Gen-Options.html)
is clear on how -ffixed-reg must behave:
```
Treat the register named reg as a fixed register; generated
code should never refer to it (except perhaps as a stack pointer,
frame pointer or in some other fixed role).
```
This implies prolog/epilog code also must not save/restore explicitly
fixed registers, even when it is callee-saved. Some projects rely on
this (GCC's) behavior.
For example,
```
void f() {
register uint64_t x28 asm("x28") = 0xee;
asm volatile("" : "+r"(x28)); // avoid mov being eliminated
}
```
should not touch x28 outside of `mov w28,#0xee`.
For riscv64, clang behaves the same as GCC, so I am inclined to believe
this is indeed a bug.
Fixes #111379.
Diffstat (limited to 'llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp')
0 files changed, 0 insertions, 0 deletions