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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2020-04-10 15:54:54 -0700 |
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| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2020-04-16 10:31:39 -0700 |
| commit | 2e94a64b57db8cb2225f70ad931d86792db7708f (patch) | |
| tree | 6843698f4342d7b36dfdddae6422cf246e289fa5 /llvm/utils/FileCheck/FileCheck.cpp | |
| parent | 3a6b60fa623da6e311b61c812932917085067cd3 (diff) | |
| download | llvm-2e94a64b57db8cb2225f70ad931d86792db7708f.zip llvm-2e94a64b57db8cb2225f70ad931d86792db7708f.tar.gz llvm-2e94a64b57db8cb2225f70ad931d86792db7708f.tar.bz2 | |
[AMDGPU] Define 16 bit SGPR subregs
These are needed as a counterpart for VGPR subregs even though
there are no scalar instructions which can operate 16 bit values.
When we are materializing a constant that is done into an SGPR
and that SGPR may/will be copied into a 16 bit VGPR subreg. Such
copy is illegal. There are also similar problems if a source
operand of a 16 bit VALU instruction is an SGPR. In addition
we need to get a register with a lo16 subregister of an SGPR
RC during selection and this fails as well.
All of that makes me believe we need these subregisters as a
syntactic glue.
Differential Revision: https://reviews.llvm.org/D78250
Diffstat (limited to 'llvm/utils/FileCheck/FileCheck.cpp')
0 files changed, 0 insertions, 0 deletions