diff options
| author | Caroline Concatto <caroline.concatto@arm.com> | 2022-11-08 12:02:04 +0000 |
|---|---|---|
| committer | Caroline Concatto <caroline.concatto@arm.com> | 2022-11-08 12:32:48 +0000 |
| commit | d917276cd8e8311df2c11a9263f4dfb760be769f (patch) | |
| tree | 4a8d00f1e66b67991afc2a189828ef652b6b67a2 /llvm/unittests/Support/ThreadLocalTest.cpp | |
| parent | 2525fddae8eda0a2520ae22fd8b36e1fc1c8ecc1 (diff) | |
| download | llvm-d917276cd8e8311df2c11a9263f4dfb760be769f.zip llvm-d917276cd8e8311df2c11a9263f4dfb760be769f.tar.gz llvm-d917276cd8e8311df2c11a9263f4dfb760be769f.tar.bz2 | |
[AArch64]SME2 Single and Multi vector Shift and Multiply instructions
This patch adds the assembly/disassembly for the following instructions:
SQRSHR (four registers): Multi-vector signed saturating rounding shift right narrow by immediate.
(two registers): Multi-vector signed saturating rounding shift right narrow by immediate.
SQRSHRN: Multi-vector signed saturating rounding shift right narrow by immediate and interleave.
SQRSHRU (four registers): Multi-vector signed saturating rounding shift right unsigned narrow by immediate.
(two registers): Multi-vector signed saturating rounding shift right unsigned narrow by immediate.
SQRSHRUN: Multi-vector signed saturating rounding shift right unsigned narrow by immediate and interleave.
UQRSHR (four registers): Multi-vector unsigned saturating rounding shift right narrow by immediate
(two registers): Multi-vector unsigned saturating rounding shift right narrow by immediate.
UQRSHRN: Multi-vector unsigned saturating rounding shift right narrow by immediate and interleave.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Reviewed By: paulwalker-arm
Differential Revision: https://reviews.llvm.org/D136150
Diffstat (limited to 'llvm/unittests/Support/ThreadLocalTest.cpp')
0 files changed, 0 insertions, 0 deletions