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author | Fraser Cormack <fraser@codeplay.com> | 2022-02-01 14:22:33 +0000 |
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committer | Fraser Cormack <fraser@codeplay.com> | 2022-02-09 07:50:15 +0000 |
commit | 6449bea508f1d1e193497697f185953769ad65e2 (patch) | |
tree | 1ed42d5b5b100170ca0c7ef6a584027d1bde529d /llvm/unittests/Support/ThreadLocalTest.cpp | |
parent | 4db88a54b6d4bd38fe38dbe57ec2a156ff3c144e (diff) | |
download | llvm-6449bea508f1d1e193497697f185953769ad65e2.zip llvm-6449bea508f1d1e193497697f185953769ad65e2.tar.gz llvm-6449bea508f1d1e193497697f185953769ad65e2.tar.bz2 |
[RISCV] Select unmasked RVV pseudos in a DAG post-process
This patch drops TableGen patterns matching all-ones masked RVV pseudos
in the case where there are fallback patterns matching the generic
masked forms to "_MASK" pseudos. This optimization is now performed with
a SelectionDAG post-processing step which peephole-optimizes these same
pseudos with all-ones masks and swaps them out to their unmasked
pseudos.
This cuts our generated ISel table down by around ~5% (~110kB) in lieu
of a far smaller auto-generated table to help with the peephole.
This only targets our custom RISCVISD::*_VL binary operator nodes, which
use the one form for both masked and unmasked variants. A similar
approach could be used for our intrinsics but we'd need to do some work,
e.g., to represent unmasked intrinsics as true-masked intrinsics at the
IR or ISel level. At a rough estimate, this could save us a further 9%
on the size of our ISel table for the binary intrinsic patterns alone.
There is no observable impact on our tests.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D118810
Diffstat (limited to 'llvm/unittests/Support/ThreadLocalTest.cpp')
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