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| author | Jianhui Li <jian.hui.li@intel.com> | 2025-07-30 16:00:40 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-30 16:00:40 -0700 |
| commit | e6f360b0ab6573bf9d3bb0e42445a20c93eea8b1 (patch) | |
| tree | c4bf0b167f14a0de478c2f48e21a767b2c8852c3 /llvm/unittests/Support/DebugLogTest.cpp | |
| parent | b9a627e6fba4137ca5411aaa416d57e28f685588 (diff) | |
| download | llvm-e6f360b0ab6573bf9d3bb0e42445a20c93eea8b1.zip llvm-e6f360b0ab6573bf9d3bb0e42445a20c93eea8b1.tar.gz llvm-e6f360b0ab6573bf9d3bb0e42445a20c93eea8b1.tar.bz2 | |
[MLIR][XeGPU] Allow load/store/prefetch uses [memref+offset] instead of tdesc (#150576)
Add variant of load/store/prefetch to allow offset. The new xegpu.load
variant accepts memref+offset, and the existing tdesc operand will be
removed in the future PR.
The semantics are combination of "creating scattered_tdesc + xegpu.load
with scattered_tdesc". The current xegpu.load accepts tdesc operand,
which encapsulates "memref+offset". This PR "fold" "memref+offset"
directly to xegpu.load replacing "tdesc". Create_tdesc will be removed
as scatter_tdesc only contains base address after offsets being taken
away, so there is no point to keep it.
```mlir
// wi level code example
%2 = xegpu.load %src[%offsets], %mask <{chunk_size = 2}> : ui64, vector<1xindex>, vector<1xi1> -> vector<2xf32>
xegpu.store %val, %src[%offsets], %mask: vector<1xf16>, memref<?xf16>, vector<1xindex>, vector<1xi1>
xegpu.prefetch %src[%0] : ui64, vector<1xindex>
```
Diffstat (limited to 'llvm/unittests/Support/DebugLogTest.cpp')
0 files changed, 0 insertions, 0 deletions