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| author | Puyan Lotfi <puyan@puyan.org> | 2018-01-31 22:04:26 +0000 |
|---|---|---|
| committer | Puyan Lotfi <puyan@puyan.org> | 2018-01-31 22:04:26 +0000 |
| commit | 43e94b15ea0c180ebb0fd3e6b697dac4564aaf60 (patch) | |
| tree | f7934a17bdee8aeebc4f8c00769b5fdd6bd1b9ff /llvm/unittests/CodeGen/MachineOperandTest.cpp | |
| parent | de07acb9a53066cb9c2a3e4bc4edd7be06db17d1 (diff) | |
| download | llvm-43e94b15ea0c180ebb0fd3e6b697dac4564aaf60.zip llvm-43e94b15ea0c180ebb0fd3e6b697dac4564aaf60.tar.gz llvm-43e94b15ea0c180ebb0fd3e6b697dac4564aaf60.tar.bz2 | |
Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:
http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html
In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.
llvm-svn: 323922
Diffstat (limited to 'llvm/unittests/CodeGen/MachineOperandTest.cpp')
| -rw-r--r-- | llvm/unittests/CodeGen/MachineOperandTest.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/unittests/CodeGen/MachineOperandTest.cpp b/llvm/unittests/CodeGen/MachineOperandTest.cpp index cedea8c..53ec5ae 100644 --- a/llvm/unittests/CodeGen/MachineOperandTest.cpp +++ b/llvm/unittests/CodeGen/MachineOperandTest.cpp @@ -80,7 +80,7 @@ TEST(MachineOperandTest, PrintSubReg) { std::string str; raw_string_ostream OS(str); MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr); - ASSERT_TRUE(OS.str() == "%physreg1.subreg5"); + ASSERT_TRUE(OS.str() == "$physreg1.subreg5"); } TEST(MachineOperandTest, PrintCImm) { |