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| author | Andrei Safronov <andrei.safronov@espressif.com> | 2022-12-26 11:49:11 +0100 |
|---|---|---|
| committer | stefan.stipanovic <stefan.stipanovic@espressif.com> | 2022-12-26 13:30:51 +0100 |
| commit | 8a6552016c97ae3c1e4fe6d18a1f5ac43a4a44c1 (patch) | |
| tree | 009f6e2d7a8427ea44eb0a56713e488dac91f6d3 /llvm/tools/llvm-strings/llvm-strings.cpp | |
| parent | 52804a7f22a20e020caacb71571e0cca712f0a12 (diff) | |
| download | llvm-8a6552016c97ae3c1e4fe6d18a1f5ac43a4a44c1.zip llvm-8a6552016c97ae3c1e4fe6d18a1f5ac43a4a44c1.tar.gz llvm-8a6552016c97ae3c1e4fe6d18a1f5ac43a4a44c1.tar.bz2 | |
[Xtensa 4/10] Add basic *td files with Xtensa architecture description
Add initial Xtensa.td file with target machine description. Add XtensaInstrInfo.td,
currently describe just susbet of Core Instructions like ALU, Processor control,
memory barrier and some move instructions. Add descriptions of the instructions
formats(XtensaInstrInfo.td) and some immediate instruction operands(XtensaOperands.td).
Add General Registers and Special Registers classes.
Differential Revision: https://reviews.llvm.org/D64830
Diffstat (limited to 'llvm/tools/llvm-strings/llvm-strings.cpp')
0 files changed, 0 insertions, 0 deletions