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author | Roman Lebedev <lebedev.ri@gmail.com> | 2022-12-26 21:46:20 +0300 |
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committer | Roman Lebedev <lebedev.ri@gmail.com> | 2022-12-26 22:54:03 +0300 |
commit | 83288f8063377f03cbcf3e89c940d2a62c855a96 (patch) | |
tree | d3f157d2a88ffb500500e17cf773332474745a6b /llvm/tools/llvm-strings/llvm-strings.cpp | |
parent | 62fc5f16405a7d39e62044bc461752f3f31bdca0 (diff) | |
download | llvm-83288f8063377f03cbcf3e89c940d2a62c855a96.zip llvm-83288f8063377f03cbcf3e89c940d2a62c855a96.tar.gz llvm-83288f8063377f03cbcf3e89c940d2a62c855a96.tar.bz2 |
[AArch64] Custom lower `ISD::ZERO_EXTEND_VECTOR_INREG`
The baseline legalization for `ISD::ZERO_EXTEND_VECTOR_INREG`
(`VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG`),
blends-in the zeros, but as mentioned e.g.
in b4bd0a404fe26071dab0854dfd9767974909c7c4,
there is no such thing for AArch64.
So some of the shuffles that would be nicely lowered
by `LowerVECTOR_SHUFFLE()`, e.g. into `ZIP1`,
would now be unrecognizable after round-tripping
through `ISD::ZERO_EXTEND_VECTOR_INREG` recognition & legalization.
The most obvious solution is to just custom-lower
`ISD::ZERO_EXTEND_VECTOR_INREG` as the `ZIP1`-with-zeros,
like it would have been originally in that test case.
Diffstat (limited to 'llvm/tools/llvm-strings/llvm-strings.cpp')
0 files changed, 0 insertions, 0 deletions