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| author | Peter Waller <peter.waller@arm.com> | 2021-04-29 15:40:34 +0000 |
|---|---|---|
| committer | Peter Waller <peter.waller@arm.com> | 2021-05-12 10:57:25 +0100 |
| commit | 6e6f9a636b1917f366821fb0a5c37cde19634c7a (patch) | |
| tree | 383712df10f2ba744ebb3aebef18efbd9233619d /llvm/tools/llvm-readobj/llvm-readobj.cpp | |
| parent | 71e66da04cf15cf47045b5d1482803197a24a75d (diff) | |
| download | llvm-6e6f9a636b1917f366821fb0a5c37cde19634c7a.zip llvm-6e6f9a636b1917f366821fb0a5c37cde19634c7a.tar.gz llvm-6e6f9a636b1917f366821fb0a5c37cde19634c7a.tar.bz2 | |
[AArch64][SVE] Improve sve.convert.to.svbool lowering
The sve.convert.to.svbool lowering has the effect of widening a logical
<M x i1> vector representing lanes into a physical <16 x i1> vector
representing bits in a predicate register.
In general, if converting to svbool, the contents of lanes in the
physical register might not be known. For sve.convert.to.svbool the new
lanes are specified to be zeroed, requiring 'and' instructions to mask
off the new lanes. For lanes coming from a ptrue or a comparison,
however, they are known to be zero.
CodeGen Before:
ptrue p0.s, vl16
ptrue p1.s
ptrue p2.b
and p0.b, p2/z, p0.b, p1.b
ret
After:
ptrue p0.s, vl16
ret
Differential Revision: https://reviews.llvm.org/D101544
Diffstat (limited to 'llvm/tools/llvm-readobj/llvm-readobj.cpp')
0 files changed, 0 insertions, 0 deletions