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authorElizaveta Noskova <159026035+enoskova-sc@users.noreply.github.com>2024-12-18 12:27:40 +0300
committerGitHub <noreply@github.com>2024-12-18 12:27:40 +0300
commit5fc8062f5d9b0c62bdb3c817182d7275d27f7527 (patch)
treefb4e709850e9cca8d13745d41bf8e2b9f6a4783c /llvm/tools/llvm-cov/SourceCoverageViewText.cpp
parent1d4453a6711394b368995c0f761015c1f6d27250 (diff)
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[llvm][RISCV] Set ScalableVector stack id in proper place (#117862)
Without this patch ScalableVector frame index property is used before assignment. More precisely, let's take a look at RISCVFrameLowering::assignCalleeSavedSpillSlots. In this function we divide callee saved registers on scalar and vector ones, based on ScalableVector property of their frame indexes: ``` ... const auto &UnmanagedCSI = getUnmanagedCSI(*MF, CSI); const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, CSI); ... ``` But we assign ScalableVector property several lines below: ``` ... auto storeRegToStackSlot = [&](decltype(UnmanagedCSI) CSInfo) { for (auto &CS : CSInfo) { // Insert the spill to the stack frame. Register Reg = CS.getReg(); const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); TII.storeRegToStackSlot(MBB, MI, Reg, !MBB.isLiveIn(Reg), CS.getFrameIdx(), RC, TRI, Register()); } }; storeRegToStackSlot(UnmanagedCSI); ... ``` Due to it, list of RVV callee saved registers will always be empty. Currently this problem doesn't appear, but if you slightly change the code and, for example, put some instructions between scalar and vector spills, the resulting code will be ill formed.
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