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authorAlex Bradbury <asb@lowrisc.org>2017-09-28 09:31:46 +0000
committerAlex Bradbury <asb@lowrisc.org>2017-09-28 09:31:46 +0000
commit5518cbfc4187564302dbc23515d812eab8e584e7 (patch)
treeb00dba8ae20855256f09990240f99d3da5758c95 /llvm/tools/llvm-cov/SourceCoverageViewText.cpp
parent0b4d10c8b3cc883e498fe6905bdb31befb8cd735 (diff)
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Teach TargetInstrInfo::getInlineAsmLength to parse .space directives with integer arguments
It's currently quite difficult to test passes like branch relaxation, which requires branches with large displacement to be generated. The .space assembler directive makes it easy to create arbitrarily large basic blocks, but getInlineAsmLength is not able to parse it and so the size of the block is not correctly estimated. Other backends (AArch64, AMDGPU) introduce options just for testing that artificially restrict the ranges of branch instructions (e.g. aarch64-tbz-offset-bits). Although parsing a single form of the .space directive feels inelegant, it does allow a more direct testing approach. This patch adapts the .space parsing code from Mips16InstrInfo::getInlineAsmLength and removes it now the extra functionality is provided by the base implementation. I want to move this functionality to the generic getInlineAsmLength as 1) I need the same for RISC-V, and 2) I feel other backends will benefit from more direct testing of large branch displacements. Differential Revision: https://reviews.llvm.org/D37798 llvm-svn: 314393
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