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| author | Craig Topper <craig.topper@sifive.com> | 2023-08-23 20:26:20 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2023-08-23 20:26:23 -0700 |
| commit | 2ad50f354a2dbd7a1c0ab0ab15723ed48d4a5b7b (patch) | |
| tree | 37e457477cc1c6b342ffb5787f2e840776128a77 /llvm/tools/llvm-cov/SourceCoverageViewText.cpp | |
| parent | 16ccba51072bbc5ff4c66f91f939163dc91e5d96 (diff) | |
| download | llvm-2ad50f354a2dbd7a1c0ab0ab15723ed48d4a5b7b.zip llvm-2ad50f354a2dbd7a1c0ab0ab15723ed48d4a5b7b.tar.gz llvm-2ad50f354a2dbd7a1c0ab0ab15723ed48d4a5b7b.tar.bz2 | |
[DAGCombiner][RISCV][AArch64][PowerPC] Restrict foldAndOrOfSETCC from using SMIN/SMAX where and OR/AND would do.
This removes some diffs created by D153502.
I'm assuming an AND/OR won't be worse than an SMIN/SMAX. For
RISC-V at least, AND/OR can be a shorter encoding than SMIN/SMAX.
It's weird that we have two different functions responsible for
folding logic of setccs, but I'm not ready to try to untangle that.
I'm unclear if the PowerPC chang is a regression or not. It looks
like it might use more registers, but I don't understand PowerPC
register so I'm not sure.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D158292
Diffstat (limited to 'llvm/tools/llvm-cov/SourceCoverageViewText.cpp')
0 files changed, 0 insertions, 0 deletions