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authorCraig Topper <craig.topper@sifive.com>2025-08-05 20:11:59 -0700
committerGitHub <noreply@github.com>2025-08-05 20:11:59 -0700
commit6ba6efea8438006be7d46ec064eb5da6dfda3d1b (patch)
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[RISCV] Simplify one of the RV32 PACK isel patterns. (#152045)
This pattern previously checked a specific variant of 4 bytes being packed that is generated by unaligned load expansion. Our individual PACK patterns don't handle that particular case because a DAG combine turns (or (or A, (shl B, 8)), (shl (or C, (shl D, 8)), 16)) into (or (or A, (shl B, 8)), (or (shl C, 16), (shl D, 24)). After this, the outer OR doesn't have a shl operand so we needed a pattern that looks through 2 layers of OR. To match this pattern we don't need to look at the (or A, (shl B, 8)) part since that part wasn't affected by the DAG combine and can be matched to PACKH by itself. It's enough to make sure that part of the pattern has zeros in the upper 16 bits. This allows tablegen to automatically generate more permutations of this pattern. The associative variant expansion is limited to 3 children.
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