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| author | Luke <luke957@foxmail.com> | 2021-02-26 22:10:30 +0800 |
|---|---|---|
| committer | Luke <luke957@foxmail.com> | 2021-03-05 10:54:51 +0800 |
| commit | d28297ff68eeecc381426416ff92a466953cd93d (patch) | |
| tree | 3e62834fa03bbec180904cf940eda36f57248ed5 /llvm/lib/Target/WebAssembly | |
| parent | 2357d29335f293ac0333dd86a0118856d586922f (diff) | |
| download | llvm-d28297ff68eeecc381426416ff92a466953cd93d.zip llvm-d28297ff68eeecc381426416ff92a466953cd93d.tar.gz llvm-d28297ff68eeecc381426416ff92a466953cd93d.tar.bz2 | |
[RISCV] Enable fixed-length vectorization of LoopVectorizer for RISC-V Vector
By implementing the method "unsigned RISCVTTIImpl::getRegisterBitWidth(bool Vector)",
fixed-length vectorization is enabled when possible. Without this method, the
"#pragma clang loop" directive is needed to enable vectorization(or the cost model
may inform LLVM that "Vectorization is possible but not beneficial").
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D97549
Diffstat (limited to 'llvm/lib/Target/WebAssembly')
0 files changed, 0 insertions, 0 deletions