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author | quic-areg <aregmi@quicinc.com> | 2025-07-18 10:27:59 -0500 |
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committer | GitHub <noreply@github.com> | 2025-07-18 10:27:59 -0500 |
commit | ac7ceb3dabfac548caa993e7b77bbadc78af4464 (patch) | |
tree | 05faf3ce6e8d2c34feedc84787d7e2011b10baf1 /llvm/lib/Target/WebAssembly/WebAssemblyTargetObjectFile.cpp | |
parent | 32f0fc597f92f98f1be81abbd07f5164377668ef (diff) | |
download | llvm-ac7ceb3dabfac548caa993e7b77bbadc78af4464.zip llvm-ac7ceb3dabfac548caa993e7b77bbadc78af4464.tar.gz llvm-ac7ceb3dabfac548caa993e7b77bbadc78af4464.tar.bz2 |
[Hexagon][llvm-objdump] Improve disassembly of Hexagon bundles (#145807)
Hexagon instructions are VLIW "bundles" of up to four instruction words
encoded as a single MCInst with operands for each sub-instruction.
Previously, the disassembler's getInstruction() returned the full
bundle, which made it difficult to work with llvm-objdump.
For example, since all instructions are bundles, and bundles do not
branch, branch targets could not be printed.
This patch modifies the Hexagon disassembler to return individual
sub-instructions instead of entire bundles, enabling correct printing of
branch targets and relocations. It also introduces
`MCDisassembler::getInstructionBundle` for cases where the full bundle
is still needed.
By default, llvm-objdump separates instructions with newlines. However,
this does not work well for Hexagon syntax:
{ inst1
inst2
inst3
inst4 <branch> } :endloop0
Instructions may be followed by a closing brace, a closing brace with
`:endloop`, or a newline. Branches must appear within the braces.
To address this, `PrettyPrinter::getInstructionSeparator()` is added and
overridden for Hexagon.
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyTargetObjectFile.cpp')
0 files changed, 0 insertions, 0 deletions