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author | Vyacheslav Levytskyy <vyacheslav.levytskyy@intel.com> | 2024-06-05 09:57:23 +0200 |
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committer | GitHub <noreply@github.com> | 2024-06-05 09:57:23 +0200 |
commit | 37cf0473ada321cc927a40e3118df26d2375e472 (patch) | |
tree | 0d21e16d9de70525352521c5f43c7e97fd2c61e5 /llvm/lib/Target/SPIRV | |
parent | 6d4fb3d3bbecbdfa1c98da3f7e09322abaec5f97 (diff) | |
download | llvm-37cf0473ada321cc927a40e3118df26d2375e472.zip llvm-37cf0473ada321cc927a40e3118df26d2375e472.tar.gz llvm-37cf0473ada321cc927a40e3118df26d2375e472.tar.bz2 |
[SPIR-V] Introduce support of '__spirv_' wrapper builtins for the SPV_INTEL_subgroups extension (#94235)
This PR Introduces support of '__spirv_' wrapper builtins for the
SPV_INTEL_subgroups extension.
Diffstat (limited to 'llvm/lib/Target/SPIRV')
-rw-r--r-- | llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 10 | ||||
-rw-r--r-- | llvm/lib/Target/SPIRV/SPIRVBuiltins.td | 15 |
2 files changed, 24 insertions, 1 deletions
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp index 424087f..956b851 100644 --- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp @@ -1020,9 +1020,17 @@ static bool generateIntelSubgroupsInst(const SPIRV::IncomingCall *Call, } const SPIRV::IntelSubgroupsBuiltin *IntelSubgroups = SPIRV::lookupIntelSubgroupsBuiltin(Builtin->Name); - MachineRegisterInfo *MRI = MIRBuilder.getMRI(); uint32_t OpCode = IntelSubgroups->Opcode; + if (Call->isSpirvOp()) { + bool IsSet = OpCode != SPIRV::OpSubgroupBlockWriteINTEL && + OpCode != SPIRV::OpSubgroupImageBlockWriteINTEL; + return buildOpFromWrapper(MIRBuilder, OpCode, Call, + IsSet ? GR->getSPIRVTypeID(Call->ReturnType) + : Register(0)); + } + + MachineRegisterInfo *MRI = MIRBuilder.getMRI(); if (IntelSubgroups->IsBlock) { // Minimal number or arguments set in TableGen records is 1 if (SPIRVType *Arg0Type = GR->getSPIRVTypeForVReg(Call->Arguments[0])) { diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td index 692234c..24c6c26 100644 --- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td +++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td @@ -1055,6 +1055,21 @@ foreach i = ["", "2", "4", "8", "16"] in { } // OpSubgroupImageBlockReadINTEL and OpSubgroupImageBlockWriteINTEL are to be resolved later on (in code) +// Multiclass used to define builtin wrappers for the SPV_INTEL_subgroups extension. +multiclass DemangledIntelSubgroupsBuiltinWrapper<string name, bits<8> numArgs, Op operation> { + def : DemangledBuiltin<!strconcat("__spirv_", name), OpenCL_std, IntelSubgroups, numArgs, numArgs>; + def : IntelSubgroupsBuiltin<!strconcat("__spirv_", name), operation>; +} + +defm : DemangledIntelSubgroupsBuiltinWrapper<"SubgroupShuffleINTEL", 2, OpSubgroupShuffleINTEL>; +defm : DemangledIntelSubgroupsBuiltinWrapper<"SubgroupShuffleDownINTEL", 3, OpSubgroupShuffleDownINTEL>; +defm : DemangledIntelSubgroupsBuiltinWrapper<"SubgroupShuffleUpINTEL", 3, OpSubgroupShuffleUpINTEL>; +defm : DemangledIntelSubgroupsBuiltinWrapper<"SubgroupShuffleXorINTEL", 2, OpSubgroupShuffleXorINTEL>; +defm : DemangledIntelSubgroupsBuiltinWrapper<"SubgroupBlockReadINTEL", 1, OpSubgroupBlockReadINTEL>; +defm : DemangledIntelSubgroupsBuiltinWrapper<"SubgroupBlockWriteINTEL", 2, OpSubgroupBlockWriteINTEL>; +defm : DemangledIntelSubgroupsBuiltinWrapper<"SubgroupImageBlockReadINTEL", 2, OpSubgroupImageBlockReadINTEL>; +defm : DemangledIntelSubgroupsBuiltinWrapper<"SubgroupImageBlockWriteINTEL", 3, OpSubgroupImageBlockWriteINTEL>; + //===----------------------------------------------------------------------===// // Class defining a builtin for group operations within uniform control flow. // It should be translated into a SPIR-V instruction using |