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| author | Craig Topper <craig.topper@sifive.com> | 2024-04-19 12:39:32 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-04-19 12:39:32 -0700 |
| commit | 016ce9ed5cd3694cbff72a768a593714913822ea (patch) | |
| tree | d0050c4e31baab5f326578d1d81dfa716e27d1ee /llvm/lib/Target/RISCV/RISCVFeatures.td | |
| parent | ce48f43f054f396fec50287cf8c7624bfaa5842a (diff) | |
| download | llvm-016ce9ed5cd3694cbff72a768a593714913822ea.zip llvm-016ce9ed5cd3694cbff72a768a593714913822ea.tar.gz llvm-016ce9ed5cd3694cbff72a768a593714913822ea.tar.bz2 | |
[RISCV] Rename FeatureRVE to FeatureStdExtE. NFC (#89174)
Planning to declare all extensions in tablegen so we can generate the
tables for RISCVISAInfo.cpp. This requires making "e" consistent with
other extensions.
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVFeatures.td')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVFeatures.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 339c039..116e5a2 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -16,6 +16,10 @@ def FeatureStdExtI : SubtargetFeature<"i", "HasStdExtI", "true", "'I' (Base Integer Instruction Set)">; +def FeatureStdExtE + : SubtargetFeature<"e", "HasStdExtE", "true", + "Implements RV{32,64}E (provides 16 rather than 32 GPRs)">; + def FeatureStdExtZic64b : SubtargetFeature<"zic64b", "HasStdExtZic64b", "true", "'Zic64b' (Cache Block Size Is 64 Bytes)">; @@ -1162,10 +1166,6 @@ def IsRV32 : Predicate<"!Subtarget->is64Bit()">, defvar RV32 = DefaultMode; def RV64 : HwMode<"+64bit", [IsRV64]>; -def FeatureRVE - : SubtargetFeature<"e", "IsRVE", "true", - "Implements RV{32,64}E (provides 16 rather than 32 GPRs)">; - def FeatureRelax : SubtargetFeature<"relax", "EnableLinkerRelax", "true", "Enable Linker relaxation.">; |