From 016ce9ed5cd3694cbff72a768a593714913822ea Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 19 Apr 2024 12:39:32 -0700 Subject: [RISCV] Rename FeatureRVE to FeatureStdExtE. NFC (#89174) Planning to declare all extensions in tablegen so we can generate the tables for RISCVISAInfo.cpp. This requires making "e" consistent with other extensions. --- llvm/lib/Target/RISCV/RISCVFeatures.td | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'llvm/lib/Target/RISCV/RISCVFeatures.td') diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 339c039..116e5a2 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -16,6 +16,10 @@ def FeatureStdExtI : SubtargetFeature<"i", "HasStdExtI", "true", "'I' (Base Integer Instruction Set)">; +def FeatureStdExtE + : SubtargetFeature<"e", "HasStdExtE", "true", + "Implements RV{32,64}E (provides 16 rather than 32 GPRs)">; + def FeatureStdExtZic64b : SubtargetFeature<"zic64b", "HasStdExtZic64b", "true", "'Zic64b' (Cache Block Size Is 64 Bytes)">; @@ -1162,10 +1166,6 @@ def IsRV32 : Predicate<"!Subtarget->is64Bit()">, defvar RV32 = DefaultMode; def RV64 : HwMode<"+64bit", [IsRV64]>; -def FeatureRVE - : SubtargetFeature<"e", "IsRVE", "true", - "Implements RV{32,64}E (provides 16 rather than 32 GPRs)">; - def FeatureRelax : SubtargetFeature<"relax", "EnableLinkerRelax", "true", "Enable Linker relaxation.">; -- cgit v1.1