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author | paperchalice <liujunchang97@outlook.com> | 2024-06-04 08:10:58 +0800 |
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committer | GitHub <noreply@github.com> | 2024-06-04 08:10:58 +0800 |
commit | 7652a59407018c057cdc1163c9f64b5b6f0954eb (patch) | |
tree | 34a730f64f9710e3043df8e967120cac8ad79d6d /llvm/lib/Target/PowerPC | |
parent | 0ea1271ee13c8c3d765904dba16dd27b91584d66 (diff) | |
download | llvm-7652a59407018c057cdc1163c9f64b5b6f0954eb.zip llvm-7652a59407018c057cdc1163c9f64b5b6f0954eb.tar.gz llvm-7652a59407018c057cdc1163c9f64b5b6f0954eb.tar.bz2 |
Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)
- Fix build with `EXPENSIVE_CHECKS`
- Remove unused `PassName::ID` to resolve warning
- Mark `~SelectionDAGISel` virtual so AArch64 backend can work properly
Diffstat (limited to 'llvm/lib/Target/PowerPC')
-rw-r--r-- | llvm/lib/Target/PowerPC/PPC.h | 2 | ||||
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 18 | ||||
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCTargetMachine.cpp | 2 |
3 files changed, 14 insertions, 8 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC.h b/llvm/lib/Target/PowerPC/PPC.h index eb8886d..94a59d1 100644 --- a/llvm/lib/Target/PowerPC/PPC.h +++ b/llvm/lib/Target/PowerPC/PPC.h @@ -78,7 +78,7 @@ class ModulePass; void initializePPCMIPeepholePass(PassRegistry&); void initializePPCExpandAtomicPseudoPass(PassRegistry &); void initializePPCCTRLoopsPass(PassRegistry &); - void initializePPCDAGToDAGISelPass(PassRegistry &); + void initializePPCDAGToDAGISelLegacyPass(PassRegistry &); void initializePPCMergeStringPoolPass(PassRegistry &); extern char &PPCVSXFMAMutateID; diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 26560dc..275b333 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -147,12 +147,10 @@ namespace { unsigned GlobalBaseReg = 0; public: - static char ID; - PPCDAGToDAGISel() = delete; explicit PPCDAGToDAGISel(PPCTargetMachine &tm, CodeGenOptLevel OptLevel) - : SelectionDAGISel(ID, tm, OptLevel), TM(tm) {} + : SelectionDAGISel(tm, OptLevel), TM(tm) {} bool runOnMachineFunction(MachineFunction &MF) override { // Make sure we re-emit a set of the global base reg if necessary @@ -447,11 +445,19 @@ private: void transferMemOperands(SDNode *N, SDNode *Result); }; + class PPCDAGToDAGISelLegacy : public SelectionDAGISelLegacy { + public: + static char ID; + explicit PPCDAGToDAGISelLegacy(PPCTargetMachine &tm, + CodeGenOptLevel OptLevel) + : SelectionDAGISelLegacy( + ID, std::make_unique<PPCDAGToDAGISel>(tm, OptLevel)) {} + }; } // end anonymous namespace -char PPCDAGToDAGISel::ID = 0; +char PPCDAGToDAGISelLegacy::ID = 0; -INITIALIZE_PASS(PPCDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) +INITIALIZE_PASS(PPCDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false) /// getGlobalBaseReg - Output the instructions required to put the /// base address to use for accessing globals into a register. @@ -7921,5 +7927,5 @@ void PPCDAGToDAGISel::PeepholePPC64() { /// FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM, CodeGenOptLevel OptLevel) { - return new PPCDAGToDAGISel(TM, OptLevel); + return new PPCDAGToDAGISelLegacy(TM, OptLevel); } diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp index 714cf69..1ef891d 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -141,7 +141,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTarget() { initializePPCExpandAtomicPseudoPass(PR); initializeGlobalISel(PR); initializePPCCTRLoopsPass(PR); - initializePPCDAGToDAGISelPass(PR); + initializePPCDAGToDAGISelLegacyPass(PR); initializePPCMergeStringPoolPass(PR); } |