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authorLu Weining <luweining@loongson.cn>2024-03-13 11:51:47 +0800
committerGitHub <noreply@github.com>2024-03-13 11:51:47 +0800
commite4edbae0aa6a9739954ee3b494b18f8c599d9d79 (patch)
treef0a13112b32a53d6451e8b506bed1baede92bc04 /llvm/lib/Target/LoongArch
parent15a55486a54183d4fc597ed86c0d49fe9482f2bd (diff)
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Revert "[llvm][LoongArch] Improve loongarch_lasx_xvpermi_q instrinsic" (#84708)
Reverts llvm/llvm-project#82984 See the discussion in https://github.com/llvm/llvm-project/pull/83540.
Diffstat (limited to 'llvm/lib/Target/LoongArch')
-rw-r--r--llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp25
1 files changed, 1 insertions, 24 deletions
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index c87f534..c13b10a 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -968,28 +968,6 @@ static SDValue checkIntrinsicImmArg(SDValue Op, unsigned ImmOp,
return SDValue();
}
-static SDValue checkAndModifyXVPERMI_QIntrinsicImmArg(SDValue Op,
- SelectionDAG &DAG) {
- SDValue Op3 = Op->getOperand(3);
- uint64_t Imm = Op3->getAsZExtVal();
- // Check the range of ImmArg.
- if (!isUInt<8>(Imm)) {
- DAG.getContext()->emitError(Op->getOperationName(0) +
- ": argument out of range.");
- return DAG.getNode(ISD::UNDEF, SDLoc(Op), Op.getValueType());
- }
-
- // For instruction xvpermi.q, only [1:0] and [5:4] bits of operands[3]
- // are used. The unused bits in operands[3] need to be set to 0 to avoid
- // causing undefined behavior on LA464.
- if ((Imm & 0x33) != Imm) {
- Op3 = DAG.getTargetConstant(Imm & 0x33, SDLoc(Op), Op3.getValueType());
- DAG.UpdateNodeOperands(Op.getNode(), Op->getOperand(0), Op->getOperand(1),
- Op->getOperand(2), Op3);
- }
- return SDValue();
-}
-
SDValue
LoongArchTargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
SelectionDAG &DAG) const {
@@ -1247,14 +1225,13 @@ LoongArchTargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::loongarch_lsx_vextrins_d:
case Intrinsic::loongarch_lasx_xvshuf4i_d:
case Intrinsic::loongarch_lasx_xvpermi_w:
+ case Intrinsic::loongarch_lasx_xvpermi_q:
case Intrinsic::loongarch_lasx_xvbitseli_b:
case Intrinsic::loongarch_lasx_xvextrins_b:
case Intrinsic::loongarch_lasx_xvextrins_h:
case Intrinsic::loongarch_lasx_xvextrins_w:
case Intrinsic::loongarch_lasx_xvextrins_d:
return checkIntrinsicImmArg<8>(Op, 3, DAG);
- case Intrinsic::loongarch_lasx_xvpermi_q:
- return checkAndModifyXVPERMI_QIntrinsicImmArg(Op, DAG);
case Intrinsic::loongarch_lsx_vrepli_b:
case Intrinsic::loongarch_lsx_vrepli_h:
case Intrinsic::loongarch_lsx_vrepli_w: