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| author | wanglei <wanglei@loongson.cn> | 2024-09-06 15:46:43 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-09-06 15:46:43 +0800 |
| commit | df93327c1ad9db7ab6c71a97bc093ce7133659d8 (patch) | |
| tree | bb8f73f691c858dac2e8c3bc2ba43960d5b4f144 /llvm/lib/Target/LoongArch | |
| parent | 4b2c950de5611a94defb00cbd66226eb02350938 (diff) | |
| download | llvm-df93327c1ad9db7ab6c71a97bc093ce7133659d8.zip llvm-df93327c1ad9db7ab6c71a97bc093ce7133659d8.tar.gz llvm-df93327c1ad9db7ab6c71a97bc093ce7133659d8.tar.bz2 | |
[LoongArch] Legalize ISD::CTPOP for GRLenVT type with LSX
Reviewed By: SixWeining
Pull Request: https://github.com/llvm/llvm-project/pull/106941
Diffstat (limited to 'llvm/lib/Target/LoongArch')
| -rw-r--r-- | llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp | 41 | ||||
| -rw-r--r-- | llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td | 4 |
2 files changed, 45 insertions, 0 deletions
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp index 95c1b15..0e17ce7 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp @@ -283,6 +283,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM, ISD::SETUGE, ISD::SETUGT}, VT, Expand); } + setOperationAction(ISD::CTPOP, GRLenVT, Legal); } // Set operations for 'LASX' feature. @@ -4488,6 +4489,44 @@ emitPseudoXVINSGR2VR(MachineInstr &MI, MachineBasicBlock *BB, return BB; } +static MachineBasicBlock *emitPseudoCTPOP(MachineInstr &MI, + MachineBasicBlock *BB, + const LoongArchSubtarget &Subtarget) { + assert(Subtarget.hasExtLSX()); + const TargetInstrInfo *TII = Subtarget.getInstrInfo(); + const TargetRegisterClass *RC = &LoongArch::LSX128RegClass; + DebugLoc DL = MI.getDebugLoc(); + MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); + Register Dst = MI.getOperand(0).getReg(); + Register Src = MI.getOperand(1).getReg(); + Register ScratchReg1 = MRI.createVirtualRegister(RC); + Register ScratchReg2 = MRI.createVirtualRegister(RC); + Register ScratchReg3 = MRI.createVirtualRegister(RC); + + BuildMI(*BB, MI, DL, TII->get(LoongArch::VLDI), ScratchReg1).addImm(0); + BuildMI(*BB, MI, DL, + TII->get(Subtarget.is64Bit() ? LoongArch::VINSGR2VR_D + : LoongArch::VINSGR2VR_W), + ScratchReg2) + .addReg(ScratchReg1) + .addReg(Src) + .addImm(0); + BuildMI( + *BB, MI, DL, + TII->get(Subtarget.is64Bit() ? LoongArch::VPCNT_D : LoongArch::VPCNT_W), + ScratchReg3) + .addReg(ScratchReg2); + BuildMI(*BB, MI, DL, + TII->get(Subtarget.is64Bit() ? LoongArch::VPICKVE2GR_D + : LoongArch::VPICKVE2GR_W), + Dst) + .addReg(ScratchReg3) + .addImm(0); + + MI.eraseFromParent(); + return BB; +} + MachineBasicBlock *LoongArchTargetLowering::EmitInstrWithCustomInserter( MachineInstr &MI, MachineBasicBlock *BB) const { const TargetInstrInfo *TII = Subtarget.getInstrInfo(); @@ -4546,6 +4585,8 @@ MachineBasicBlock *LoongArchTargetLowering::EmitInstrWithCustomInserter( case LoongArch::PseudoXVINSGR2VR_B: case LoongArch::PseudoXVINSGR2VR_H: return emitPseudoXVINSGR2VR(MI, BB, Subtarget); + case LoongArch::PseudoCTPOP: + return emitPseudoCTPOP(MI, BB, Subtarget); } } diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td index 659ba38..e7ac9f3 100644 --- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td @@ -1238,6 +1238,10 @@ def PseudoVBZ_W : VecCond<loongarch_vall_zero, v4i32>; def PseudoVBZ_D : VecCond<loongarch_vall_zero, v2i64>; def PseudoVBZ : VecCond<loongarch_vany_zero, v16i8>; +let usesCustomInserter = 1 in +def PseudoCTPOP : Pseudo<(outs GPR:$rd), (ins GPR:$rj), + [(set GPR:$rd, (ctpop GPR:$rj))]>; + } // Predicates = [HasExtLSX] multiclass PatVr<SDPatternOperator OpNode, string Inst> { |