diff options
| author | Serge Pavlov <sepavloff@gmail.com> | 2024-02-24 20:25:21 +0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-02-24 20:25:21 +0700 |
| commit | 00c0638b5613912a7d1b65c8789bbb8ad1003115 (patch) | |
| tree | f11e510e9d787a7a125457a64c12ece2ba3f8050 /llvm/lib/Target/AArch64/AArch64InstrInfo.td | |
| parent | 60a904b2ad9842b93cc5fa0ad5bda5e22c550b7e (diff) | |
| download | llvm-00c0638b5613912a7d1b65c8789bbb8ad1003115.zip llvm-00c0638b5613912a7d1b65c8789bbb8ad1003115.tar.gz llvm-00c0638b5613912a7d1b65c8789bbb8ad1003115.tar.bz2 | |
[AArch64] Intrinsics aarch64_{get,set}_fpsr (#81867)
Two new intrinsics are introduced to read/write FPSR. They are similar
to the existing intrinsics aarch64_{get,set}_fpcr.
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64InstrInfo.td')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.td | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 8e73f57..e73bc0d 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -1805,7 +1805,7 @@ def HWASAN_CHECK_MEMACCESS_SHORTGRANULES : Pseudo< // The virtual cycle counter register is CNTVCT_EL0. def : Pat<(readcyclecounter), (MRS 0xdf02)>; -// FPCR register +// FPCR and FPSR registers. let Uses = [FPCR] in def MRS_FPCR : Pseudo<(outs GPR64:$dst), (ins), [(set GPR64:$dst, (int_aarch64_get_fpcr))]>, @@ -1817,6 +1817,17 @@ def MSR_FPCR : Pseudo<(outs), (ins GPR64:$val), PseudoInstExpansion<(MSR 0xda20, GPR64:$val)>, Sched<[WriteSys]>; +let Uses = [FPSR] in +def MRS_FPSR : Pseudo<(outs GPR64:$dst), (ins), + [(set GPR64:$dst, (int_aarch64_get_fpsr))]>, + PseudoInstExpansion<(MRS GPR64:$dst, 0xda21)>, + Sched<[WriteSys]>; +let Defs = [FPSR] in +def MSR_FPSR : Pseudo<(outs), (ins GPR64:$val), + [(int_aarch64_set_fpsr i64:$val)]>, + PseudoInstExpansion<(MSR 0xda21, GPR64:$val)>, + Sched<[WriteSys]>; + // Generic system instructions def SYSxt : SystemXtI<0, "sys">; def SYSLxt : SystemLXtI<1, "sysl">; |