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| author | Dmitry Preobrazhensky <dmitri.preobrazhenski@gmail.com> | 2022-12-20 14:01:37 +0300 |
|---|---|---|
| committer | Dmitry Preobrazhensky <dmitri.preobrazhenski@gmail.com> | 2022-12-20 14:03:46 +0300 |
| commit | d9daee5a669832586c59e92223cae5600238b4cf (patch) | |
| tree | 0ee7bcf206f3e73f22279b4aa76c98cbcd6db2aa /llvm/lib/Support/TargetParser.cpp | |
| parent | ff302f850242b7f5e1fc48235471b8273c421236 (diff) | |
| download | llvm-d9daee5a669832586c59e92223cae5600238b4cf.zip llvm-d9daee5a669832586c59e92223cae5600238b4cf.tar.gz llvm-d9daee5a669832586c59e92223cae5600238b4cf.tar.bz2 | |
[AMDGPU][DOC][NFC] Update assembler syntax description
Summary of changes:
- Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205).
- Small improvements and clarifications.
- Correct typos.
Diffstat (limited to 'llvm/lib/Support/TargetParser.cpp')
0 files changed, 0 insertions, 0 deletions