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authorCraig Topper <craig.topper@sifive.com>2021-06-08 09:31:30 -0700
committerCraig Topper <craig.topper@sifive.com>2021-06-08 09:43:43 -0700
commit8b4c80d380a681e6ea6ea60e9d9f9424e7782980 (patch)
tree04090c1f56b2232f9487f627d95024cc35aa83a0 /llvm/lib/Support/TargetParser.cpp
parent71fb98e0c1de97c8ba2aa3292447b0c5d0f248d5 (diff)
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Further improve register allocation for vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv.
The first source has the same EEW as the destination, but we're using earlyclobber which prevents them from ever being the same register. This patch attempts to work around this. -For unmasked .wv, add a special TIED pseudo that pretends like the first operand and the destination must be the same register. This disables the earlyclobber for that source. Mark the instruction as convertible to 3 address form which will switch it to the original untied pseudo when the TwoAddressInstructionPass decides that keeping them tied would require an extra copy. This uses code in RISCVInstrInfo.cpp to do the conversion to the untied opcode. The untie test case show that we can generate the untied version. Not sure it was profitable to do it in this case, but they have really simple IR. Reviewed By: arcbbb Differential Revision: https://reviews.llvm.org/D103552
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