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authorKrzysztof Drewniak <Krzysztof.Drewniak@amd.com>2023-02-07 21:46:11 +0000
committerKrzysztof Drewniak <Krzysztof.Drewniak@amd.com>2023-05-12 16:21:01 +0000
commit0bc739a4ae84f44d9bb0b3b8f9505772449859a9 (patch)
treeab3c0de544348b65bb2ba31ac3ab760d8eb37431 /llvm/lib/Support/StringRef.cpp
parent1dedc96d04c82e29fff18ee3b875505a158ff93c (diff)
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[GlobalISel] Handle ptr size != index size in IRTranslator, CodeGenPrepare
While the original motivation for this patch (address space 7 on AMDGPU) has been reworked and is not presently planned to reach IR translation, the incorrect (by the spec) handling of index offset width in IR translation and CodeGenPrepare is likely to trip someone - possibly future AMD, since we have a p7:160:256:256:32 now, so we convert to the other API now. Reviewed By: aemerson, arsenm Differential Revision: https://reviews.llvm.org/D143526
Diffstat (limited to 'llvm/lib/Support/StringRef.cpp')
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