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| author | Md Asghar Ahmad Shahid <md.asghar.ahmad.shahid@intel.com> | 2025-08-08 10:13:09 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-08-08 10:13:09 +0530 |
| commit | 856a8b5ef9f40361f14b488a5dced9e9989f6fa8 (patch) | |
| tree | 2b68dd4522ba0bbc6c418b9ae9f2b2f2dc705200 /llvm/lib/MC/MCDisassembler | |
| parent | 0720af8c24f1e11217a6492fed5e3f60c0a02a19 (diff) | |
| download | llvm-856a8b5ef9f40361f14b488a5dced9e9989f6fa8.zip llvm-856a8b5ef9f40361f14b488a5dced9e9989f6fa8.tar.gz llvm-856a8b5ef9f40361f14b488a5dced9e9989f6fa8.tar.bz2 | |
[mlir][linalg] Add mixed precision folding pattern in vectorize_children_and_apply_patterns TD Op (#148684)
In case of mixed precision inputs, the inputs are generally casted to
match output type thereby introduces arith.extFOp/extIOp instructions.
Folding such pattern into vector.contract is desirable for HW having
mixed precision ISA support.
This patch adds folding of mixed precision pattern into vector.contract
optionaly which can be enabled using attribute
`fold_type_extensions_into_contract`.
Diffstat (limited to 'llvm/lib/MC/MCDisassembler')
0 files changed, 0 insertions, 0 deletions