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| author | Craig Topper <craig.topper@sifive.com> | 2022-02-01 21:07:02 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-02-01 21:07:03 -0800 |
| commit | 7f6441f96e12798ed63290fff436f347f6aca3aa (patch) | |
| tree | e90c9f1f946212f79fdd33dbd2c67f693120f334 /llvm/lib/IR/ModuleSummaryIndex.cpp | |
| parent | 42f87a0354562b6bfb3a35480677ff07c377d482 (diff) | |
| download | llvm-7f6441f96e12798ed63290fff436f347f6aca3aa.zip llvm-7f6441f96e12798ed63290fff436f347f6aca3aa.tar.gz llvm-7f6441f96e12798ed63290fff436f347f6aca3aa.tar.bz2 | |
[TableGen][RISCV] Relax a restriction in generating patterns for commutable SDNodes.
Previously, all children would be checked to see if any were an
explicit Register. If anywhere no commutable patterns would be
generated. This patch loosens the restriction to only check the
children that are being commuted.
Digging back through history, this code predates the existence of
commutable intrinsics and commutable SDNodes with more than 2
operands. At that time the loop would count the number of children that
weren't registers and if that was equal to 2 it would allow commuting.
I don't think this loop was re-considered when commutable
intrinsics were added or when we allowed SDNodes with more than 2
operands.
This important for RISCV were our isel patterns have a V0 mask
operand after the commutable operands on some RISCVISD opcodes.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D117955
Diffstat (limited to 'llvm/lib/IR/ModuleSummaryIndex.cpp')
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