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| author | Nikita Popov <nikita.ppv@gmail.com> | 2020-01-21 21:48:07 +0100 |
|---|---|---|
| committer | Nikita Popov <nikita.ppv@gmail.com> | 2020-01-30 18:40:24 +0100 |
| commit | 70d345e687caba4ac1f95655c6924dfa91e0083f (patch) | |
| tree | 8323e49db4b241e96035cd2fb48dc56125ccfc0b /llvm/lib/IR/ModuleSummaryIndex.cpp | |
| parent | 3ae11b42818363f70b3c6b0246bb617e35709c58 (diff) | |
| download | llvm-70d345e687caba4ac1f95655c6924dfa91e0083f.zip llvm-70d345e687caba4ac1f95655c6924dfa91e0083f.tar.gz llvm-70d345e687caba4ac1f95655c6924dfa91e0083f.tar.bz2 | |
[AArch64][ARM] Always expand ordered vector reductions (PR44600)
fadd/fmul reductions without reassoc are lowered to
VECREDUCE_STRICT_FADD/FMUL nodes, which don't have legalization
support. Until that is in place, expand these intrinsics on
ARM and AArch64. Other targets always expand the vector reduction
intrinsics.
Additionally expand fmax/fmin reductions without nonan flag on
AArch64, as the backend asserts that the flag is present when
lowering VECREDUCE_FMIN/FMAX.
This fixes https://bugs.llvm.org/show_bug.cgi?id=44600.
Differential Revision: https://reviews.llvm.org/D73135
Diffstat (limited to 'llvm/lib/IR/ModuleSummaryIndex.cpp')
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