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authorChristudasan Devadasan <christudasan.devadasan@amd.com>2024-09-30 19:55:42 +0530
committerGitHub <noreply@github.com>2024-09-30 19:55:42 +0530
commitac0f64f06d67a93817ccd9a3c529ad40920115c9 (patch)
tree7e6fc105fe60bc0c5f0dec039902daf6c76f8149 /llvm/lib/IR/Function.cpp
parentbfde17834dd9bd30da8f56166cd545f566f64895 (diff)
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[AMDGPU] Split vgpr regalloc pipeline (#93526)
Allocating wwm-registers and per-thread VGPR operands together imposes many challenges in the way the registers are reused during allocation. There are times when regalloc reuses the registers of regular VGPRs operations for wwm-operations in a small range leading to unwantedly clobbering their inactive lanes causing correctness issues that are hard to trace. This patch splits the VGPR allocation pipeline further to allocate wwm-registers first and the regular VGPR operands in a separate pipeline. The splitting would ensure that the physical registers used for wwm allocations won't take part in the next allocation pipeline to avoid any such clobbering.
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