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author | WANG Xuerui <git@xen0n.name> | 2023-07-18 15:47:50 +0800 |
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committer | Weining Lu <luweining@loongson.cn> | 2023-07-18 15:50:20 +0800 |
commit | 294bee106589a8ec94e9a75f435698a478147aee (patch) | |
tree | a84a9a6d0f1afdb95405de7a1cd4cb4df1988e36 /llvm/lib/IR/Function.cpp | |
parent | 6ff9761a69df24d33f7c1047a956911bf28a754b (diff) | |
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[LoongArch][NFC] Consistently derive instruction mnemonics from TableGen record names
The recent D154183 and D154195 have introduced a simpler way to specify
instruction mnemonics: by leveraging TableGen's `NAME` and string
processing features, the mnemonics can be automatically derived from the
respective TableGen record names. LoongArch instructions don't have
"strange" characters in their names, so this approach can be applied to
all the other instructions.
A `deriveInsnMnemonic` helper class, modeled after the LSX/LASX mnemonic
derivation logic, has been added, and all non-pseudo instruction formats
are converted to use it, losing their `opstr/opcstr` arguments in the
process.
There are minor differences that are worth mentioning though:
* The atomic instructions with implicit data barriers have an underscore
(`_`) in their mnemonics, that will get converted to a period (`.`) if
not specially handled. Double-underscore (`__`) in record names are
converted to a single underscore in the resulting mnemonic; the
definitions are tweaked accordingly.
* Various duplicated FP instructions need special handling, mainly
because of the need to handle both FPR32 and FPR64 classes for a
single hardware instruction. The substrings `_xS`, `_xD` and `_64` are
additionally dropped before deriving FP instructions' mnemonics.
All of these are pure refactoring, no functional change.
Reviewed By: SixWeining
Differential Revision: https://reviews.llvm.org/D154916
Diffstat (limited to 'llvm/lib/IR/Function.cpp')
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