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author | Jim Lin <jim@andestech.com> | 2025-07-25 11:29:17 +0800 |
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committer | GitHub <noreply@github.com> | 2025-07-25 11:29:17 +0800 |
commit | 4e3266fb6e40dedf99e25693e02f358de998ae69 (patch) | |
tree | 37f68fca85dc57bcf4f5fe14a01ae38e1c58f1b7 /llvm/lib/ExecutionEngine/Orc/ThreadSafeModule.cpp | |
parent | b0dea47ae613b5d4167058ebef6b91b92dea8488 (diff) | |
download | llvm-4e3266fb6e40dedf99e25693e02f358de998ae69.zip llvm-4e3266fb6e40dedf99e25693e02f358de998ae69.tar.gz llvm-4e3266fb6e40dedf99e25693e02f358de998ae69.tar.bz2 |
[RISCV] Implement load/store support for XAndesBFHCvt (#150350)
We use `lh` to load 2 bytes from memory into a gpr, then mask this gpr
with -65536 to emulate nan-boxing behavior, and then the value in gpr is
moved to fpr using `fmv.w.x`.
To move the value back from fpr to gpr, we use `fmv.x.w` and finally,
`sh` is used to store the lower 2 bytes back to memory.
If zfh is enabled at the same time, we can just use flh/fsw to
load/store bf16 directly.
Diffstat (limited to 'llvm/lib/ExecutionEngine/Orc/ThreadSafeModule.cpp')
0 files changed, 0 insertions, 0 deletions