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| author | Dmitry Bushev <dmitry.bushev@syntacore.com> | 2022-11-22 14:52:10 +0300 |
|---|---|---|
| committer | Anton Sidorenko <anton.sidorenko@syntacore.com> | 2022-11-22 16:42:44 +0300 |
| commit | 95ef005230e9f793aeb84e2f5ee58571698aace6 (patch) | |
| tree | 7342bbb93c72723eb1ace6802568858107276241 /llvm/lib/CodeGen/SelectOptimize.cpp | |
| parent | faa9be75ee9bfefa6a435f6570997ec3dd3657a3 (diff) | |
| download | llvm-95ef005230e9f793aeb84e2f5ee58571698aace6.zip llvm-95ef005230e9f793aeb84e2f5ee58571698aace6.tar.gz llvm-95ef005230e9f793aeb84e2f5ee58571698aace6.tar.bz2 | |
[RISCV][NFC] Mark rs1 in most memory instructions as memory operand.
Marking rs1 (memory offset base) as memory operand provides additional
semantic value to this operand that can be used by different tools
(e.g. llvm-exegesis).
This change does not affect neigther Isel nor assembler. However it
required some tweaks in tablegen compressed inst emmiter.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D136847
Diffstat (limited to 'llvm/lib/CodeGen/SelectOptimize.cpp')
0 files changed, 0 insertions, 0 deletions