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| author | chrisPyr <32153107+chrisPyr@users.noreply.github.com> | 2025-03-03 14:46:33 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-03-03 13:46:33 +0700 |
| commit | 71f4c7dabec0f32b2d475e8e08f0da99628a067c (patch) | |
| tree | 855a0b24f32551f0a9de9f1404826adbac111fb5 /llvm/lib/CodeGen/MachineScheduler.cpp | |
| parent | 1b043c25573aa0b13ad4241c641c38ca26f26bc1 (diff) | |
| download | llvm-71f4c7dabec0f32b2d475e8e08f0da99628a067c.zip llvm-71f4c7dabec0f32b2d475e8e08f0da99628a067c.tar.gz llvm-71f4c7dabec0f32b2d475e8e08f0da99628a067c.tar.bz2 | |
[NFC]Make file-local cl::opt global variables static (#126486)
#125983
Diffstat (limited to 'llvm/lib/CodeGen/MachineScheduler.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/MachineScheduler.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index d67e4ef..4ee8e12 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -90,7 +90,7 @@ cl::opt<MISched::Direction> PreRADirection( clEnumValN(MISched::Bidirectional, "bidirectional", "Force bidirectional pre reg-alloc list scheduling"))); -cl::opt<MISched::Direction> PostRADirection( +static cl::opt<MISched::Direction> PostRADirection( "misched-postra-direction", cl::Hidden, cl::desc("Post reg-alloc list scheduling direction"), cl::init(MISched::Unspecified), @@ -102,9 +102,9 @@ cl::opt<MISched::Direction> PostRADirection( clEnumValN(MISched::Bidirectional, "bidirectional", "Force bidirectional post reg-alloc list scheduling"))); -cl::opt<bool> -DumpCriticalPathLength("misched-dcpl", cl::Hidden, - cl::desc("Print critical path length to stdout")); +static cl::opt<bool> + DumpCriticalPathLength("misched-dcpl", cl::Hidden, + cl::desc("Print critical path length to stdout")); cl::opt<bool> VerifyScheduling( "verify-misched", cl::Hidden, |