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| author | Luke Lau <luke@igalia.com> | 2024-07-24 11:52:54 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-07-24 11:52:54 +0800 |
| commit | b91c75fcaeea47d54ac5d15b45f079bf44681dc4 (patch) | |
| tree | 805c1e9e4800a2c1d00011de5362420f490a1e9b /llvm/lib/CodeGen/MachinePipeliner.cpp | |
| parent | c49837f5f688ff2cd70ecc6d5aefd71af2afb22b (diff) | |
| download | llvm-b91c75fcaeea47d54ac5d15b45f079bf44681dc4.zip llvm-b91c75fcaeea47d54ac5d15b45f079bf44681dc4.tar.gz llvm-b91c75fcaeea47d54ac5d15b45f079bf44681dc4.tar.bz2 | |
[RISCV] Add unit strided load/store to whole register peephole (#100116)
This adds a new vector peephole that converts unmasked, VLMAX
vleN.v/vseN.v to their whole register equivalents.
It replaces the existing tablegen patterns on ISD::LOAD/ISD::STORE and
is a bit more general since it also catches VP loads and stores and
@llvm.riscv intrinsics.
The heavy lifting of detecting a VLMAX AVL and an all-ones mask is
already taken care of by existing peepholes.
Diffstat (limited to 'llvm/lib/CodeGen/MachinePipeliner.cpp')
0 files changed, 0 insertions, 0 deletions