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authorMalaySanghiIntel <148750629+MalaySanghiIntel@users.noreply.github.com>2024-03-05 13:21:43 +0530
committerGitHub <noreply@github.com>2024-03-05 15:51:43 +0800
commit0e337c67c8b9b0e04fb47712faba204c8d999af7 (patch)
tree50afde6e72409b728b4a9e412be291b72e08888f /llvm/lib/CodeGen/MachinePipeliner.cpp
parenteaa9ef678c63bf392ec2d5b736605db7ea7e7338 (diff)
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Replace copy with a reference. (#82485)
These are relatively larger structures and we don't update them so ref should be fine
Diffstat (limited to 'llvm/lib/CodeGen/MachinePipeliner.cpp')
-rw-r--r--llvm/lib/CodeGen/MachinePipeliner.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index 1bda19b..d8cb681 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -1334,7 +1334,7 @@ private:
Register Reg = getLoopPhiReg(*MI, OrigMBB);
UpdateTargetRegs(Reg);
} else {
- for (auto Use : ROMap.find(MI)->getSecond().Uses)
+ for (auto &Use : ROMap.find(MI)->getSecond().Uses)
UpdateTargetRegs(Use.RegUnit);
}
}
@@ -1438,7 +1438,7 @@ private:
const unsigned Iter = I - Stage;
- for (auto Def : ROMap.find(MI)->getSecond().Defs)
+ for (auto &Def : ROMap.find(MI)->getSecond().Defs)
InsertReg(LiveRegSets[Iter], Def.RegUnit);
for (auto LastUse : LastUses[MI]) {